PDI1394P21 datasheet(5/28 Pages) PHILIPS

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Philips Semiconductors

Objective specification

PDI1394P21

3-port physical layer interface

1999 Jul 09

Name

Description

I/O

Pin Numbers

Pin Type

/RESET

CMOS 5V tol

Logic reset input. Asserting this terminal low resets the internal logic. An

internal pull-up resistor to VDD is provided so only an external

delay capacitor in parallel with a resistor is required for proper power-up

operation. For more information, refer to Section 17.3. This input is

otherwise a standard logic input, and can also be driven by an

open-drain type driver.

R0, R1

Bias

66, 67

—

Current setting resistor terminals. These terminals are connected to

an external resistance to set the internal operating currents and

cable driver output currents. A resistance of 6.34 k

Ω ±1% is required to

meet the IEEE Std 1394–1995 output voltage limits.

SYSCLK

CMOS

System clock output. Provides a 49.152 MHz clock signal, synchronized

with data transfers, to the LLC.

TEST0

CMOS

Test control input. This input is used in manufacturing tests of the

PDI1394P21. For normal use, this terminal should be tied to GND.

TEST1

CMOS

Test control input. This input is used in manufacturing tests of the

PDI1394P21. For normal use, this terminal should be tied to GND.

TPA0+,

TPA1+,

TPA2+

Cable

45, 52, 58

I/O

Twisted-pair cable A differential signal terminals. Board traces from each

pair of positive and negative differential signal terminals should be kept

TPA0–,

TPA1–,

TPA2–

Cable

44, 51, 57

I/O

matched and as short as possible to the external load resistors and to

the cable connector.

TPB0+,

TPB1+,

TPB2+

Cable

43, 50, 56

I/O

Twisted-pair cable B differential signal terminals. Board traces from each

pair of positive and negative differential signal terminals should be kept

TPB0–,

TPB1–,

TPB2–

Cable

42, 49, 55

I/O

matched and as short as possible to the external load resistors and to

the cable connector.

TPBIAS0,

TPBIAS1,

TPBIAS2

Cable

46, 53, 59

I/O

Twisted-pair bias output. This provides the 1.86V nominal bias voltage

needed for proper operation of the twisted-pair cable drivers and

receivers, and for signaling to the remote nodes that there is an active

cable connection. Each of these terminals must be decoupled with a

0.3

µF–1 µF capacitor to ground.

XO, XI

Crystal

77, 76

—

Crystal oscillator inputs. These terminals connect to a 24.576 MHz

parallel resonant fundamental mode crystal. The optimum values for the

external shunt capacitors are dependent on the specifications of the

crystal used. Can also be driven by an external clock generator (leave

XO unconnected in this case).

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