ISO1228DFBR datasheet(13/44 Pages) TI1

13 / 44 page

(Over recommended operating conditions unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

tPLH

Propagation delay time for low to high

transition

24-VPk-Pk clock signal on IN pin with 10-ns

rise and fall time, RTHR = 0 Ω. Parallel

output mode.

F1=low, F0=low; Filter Register setting:

0xxx

780

tPHL

Propagation delay time for high to low

transition

24-VP-P clock signal on IN pin with 10-ns

rise and fall time, RTHR = 0 Ω. Parallel

output mode.

F1=low, F0=low; Filter Register setting:

0xxx

900

tsk(p)

Pulse skew |tPHL - tPLH|

24-VP-P clock signal on IN pin with 10-ns

rise and fall time, RTHR = 0 Ω. Parallel

output mode.

335

tUI

Minimum pulse width

Parallel output mode.

F1=low, F0=low; Filter Register setting:

0xxx

660

tPHZ

Disable propagation delay, high-to-high

impedance output

VIN = 24 V, Pull down resistor of 1kΩ on

OUTx. Parallel output mode

tPLZ

Disable propagation delay, low-to-high

impedance output

VIN = 0 V, Pull up resistor of 1kΩ on OUTx.

Parallel output mode

tPZH

Enable propagation delay, high

impedance-to-high output

VIN = 24 V, Pull down resistor of 1kΩ on

OUTx. Parallel output mode

µs

tPZL

Enable propagation delay, high

impedance-to-low output

VIN = 0 V, Pull up resistor of 1kΩ on OUTx.

Parallel output mode

1.5

2.6

µs

CMTI

Common mode transient immunity

F1=low, F0=low; Filter Register setting:

0xxx

kV/µs

DIGITAL LOW PASS FILTER

TFILT

Input Digital Low Pass Filter Averaging

Time

F1=low, F0=low; Filter Register setting:

0xxx

F1=low, F0=float; Filter Register setting:

1000

µs

F1=low, F0=high; Filter Register setting:

1001

µs

F1=float, F0=low; Filter Register setting:

1010

200

µs

F1=float, F0=float; Filter Register setting:

1011

F1=float, F0=high; Filter Register setting:

1100

2.5

F1=high, F0=low; Filter Register setting:

1101

F1=high, F0=float; Filter Register setting:

1110

F1=high, F0=high; Filter Register setting:

1111

100

TFILTWB

Input Filter for Wire-break Detection

SPI TIMING - 2.25 V to 5.5 V

FSCLK

SCLK Frequency, VCC1 = 2.25 V to 5.5 V

MHz

TSCLK

SCLK Bit Period

TSCLKH

SCLK High Pulse Width

TSCLKL

SCLK Low Pulse Width

TDO

SCLK output to SDO valid

4.5

12.5

TCSW

Chip Select 'High' Pulse Width

250

www.ti.com

ISO1228

SLLSFN5A – JUNE 2023 – REVISED FEBRUARY 2024

Submit Document Feedback

Product Folder Links: ISO1228

ISO1228DFBR Datasheet(PDF) 13 Page - Texas Instruments

ISO1228DFBR Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL