MPC8313CVRAFF datasheet(31/88 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.3.2

MII Management AC Electrical Specifications

Table 31 provides the MII management AC timing specifications.

Figure 14 shows the MII management AC timing diagram.

Figure 14. MII Management Interface Timing Diagram

Table 31. MII Management AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 10% or 2.5 V ± 5%

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—

400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDKHDX

—

170

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

—

MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes

management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data

hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the

valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

MDIO

(Input)

(Output)

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