ADP3197 datasheet(13/32 Pages) AD

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ADP3197

Rev. 0 | Page 13 of 32

CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-

OFF PROTECTION

The ADP3197 compares a programmable current limit setpoint

to the voltage from the output of the current sense amplifier.

The level of current limit is set with the resistor from the ILIMIT

pin to ground. During operation, the current from ILIMIT is

equal to 2/3 IREF, giving 10 μA normally.

This current, through the external resistor, sets the ILIMIT

voltage, which is internally scaled to give a current limit threshold

of 82.6 mV/V. If the difference in voltage between CSREF and

CSCOMP rises above the current limit threshold, the internal

current limit amplifier controls the internal COMP voltage to

maintain the average output current at the limit.

If the limit is reached and TD3 has completed, a latch-off delay

time starts and the controller shuts down if the fault is not removed.

The current limit delay time shares the DELAY pin timing

capacitor with the start-up sequence timing. However, during

current limit, the DELAY pin current is reduced to IREF/4.

A comparator monitors the DELAY voltage and shuts off the

controller when the voltage reaches 1.7 V. The current limit latch-

off delay time is, therefore, set by the current of IREF/4, charging

the delay capacitor from 0 V to 1.7 V. This delay is four times

longer than the delay time during the start-up sequence. The

current limit delay time starts only after TD3 has completed.

If there is a current limit during startup, the ADP3197 goes

through TD1 to TD3 and then starts the latch-off time. Because

the controller continues to cycle the phases during the latch-off

delay time, if the short is removed before the 1.7 V threshold is

reached, the controller returns to normal operation and the DELAY

capacitor is reset to GND.

The latch-off function can be reset either by removing and

reapplying the supply voltage to the ADP3197 or by toggling the

EN pin low for a short time. To disable the short-circuit latch-

off function, an external resistor should be placed in parallel

with CDLY.

This prevents the DELAY capacitor from charging up to the 1.7 V

threshold. The addition of this resistor causes a slight increase

in the delay times.

During startup, when the output voltage is below 200 mV,

a secondary current limit is active. This is necessary because

the voltage swing of CSCOMP cannot go below ground. This

secondary current limit controls the internal COMP voltage to

the PWM comparators to 1.5 V. This limits the voltage drop

across the low-side MOSFETs through the current balance

circuitry.

An inherent per phase current limit protects individual phases

if one or more phases stop functioning because of a faulty

component. This limit is based on the maximum normal mode

COMP voltage. Typical overcurrent latch-off waveforms are

shown in Figure 9.

CH1 1.00V

CH2 2.00V

CH3 5.00V

CH4 10.0V

M2.00ms

A CH1

660mV

Figure 9. Overcurrent Latch-Off Waveforms

Channel 1: CSREF, Channel 2: DELAY,

Channel 3: COMP, Channel 4: Phase 1 Switch Node

DYNAMIC VID

The ADP3197 has the ability to respond to dynamically

changing VID inputs while the controller is running. This

allows the output voltage to change while the supply is running

and supplying current to the load. This is commonly referred to

as VID on-the-fly (OTF). A VID OTF can occur under either

light or heavy load conditions. The processor signals the controller

by changing the VID inputs in multiple steps from the start

code to the finish code. This change can be positive or negative.

When a VID input changes state, the ADP3197 detects the

change and ignores the DAC inputs for a minimum of 400 ns.

This time prevents a false code due to logic skew while the six

VID inputs are changing. Additionally, the first VID change

initiates the power-good and crowbar blanking functions for

a minimum of 250 μs to prevent a false power-good or crowbar

event. Each VID change resets the internal timer.

POWER-GOOD MONITORING

The power-good comparator monitors the output voltage via

the CSREF pin. The PWRGD pin is an open-drain output whose

high level (when connected to a pull-up resistor) indicates that

the output voltage is within the nominal limits defined in the

Power-Good Comparator section of the Specifications table,

based on the VID voltage setting. PWRGD goes low if the

output voltage is outside of this specified range.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD3) based on the DELAY timer. Prior to the SS

voltage reaching the programmed VID DAC voltage and the

PWRGD masking time finishing, the PWRGD pin is held low.

Once the SS pin is within 50 mV of the programmed DAC

voltage, the capacitor on the DELAY pin begins to charge up. A

comparator monitors the DELAY voltage and enables PWRGD

when the voltage reaches 1.7 V. The PWRGD delay time is,

therefore, set by a current of IREF charging a capacitor from 0

V to 1.7 V.

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