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ADP3197 Datasheet(PDF) 21 Page - Analog Devices |
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ADP3197 Datasheet(HTML) 21 Page - Analog Devices |
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21 / 32 page  ADP3197 Rev. 0 | Page 21 of 32 A lower limit is based on meeting the capacitance for load release for a given maximum load step (ΔIO) and a maximum allowable overshoot. The total amount of load release voltage is given as ΔVO = ΔIO × ROD. () ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − × × × ≥ Z VID OD O MIN X C V R n I L C Δ (20) () ≤ MAX X C (21) Z O V VID V VID V 2 O 2 C L nKR V V t V V R nK L − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × + × × 1 1 2 where ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ − = V ERR V V n K 1 To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the dynamic input droop resistance (ROD). If CX(MIN) is larger than CX(MAX), the system cannot meet the VID on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). This example uses 18, 10 μF 1206 MLC capacitors (CZ = 180 μF). The VID on-the-fly step change is 1.3 V to 0.6 V (making VV = 0.7 V) in 100 μs with a settling error of 2.5 mV. ≈ The maximum allowable load release overshoot for this example is 3%. Therefore, solving for the bulk capacitance yields () mF 564 . 5 μF 180 V 3 . 1 m 25 . 1 3 A 70 nH 400 = ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ − × Ω × × ≤ MIN X C (22) () () × × × × × ≤ V 3 . 1 Ω m 25 . 1 5 . 3 3 mV 700 nH 400 2 2 MAX X C − ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ × × × × × + 1 nH 400 mV 700 Ω m 25 . 1 5 . 3 3 V 3 1 μs 100 1 2 . 180 μF = 19.23 mF where K = 3.5. Using 10, 560 μF Al-Poly capacitors with a typical ESR of 6 mΩ each yields CX = 5.6 mF with an RX = 0.6 mΩ. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit high frequency ringing during a load change. This is tested using () pH 562 2 mΩ 25 . 1 μF 180 2 = × × ≤ × × ≤ X 2 2 O Z X L Q R C L (23) where Q2 is limited to 2 to ensure a critically damped system. In this example, LX is approximately 240 pH for the 10 Al-Poly capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors needs to be increased, or lower ESL bulks must be used if there is excessive undershoot during a load transient. For this multimode control technique, all ceramic designs can be used providing the conditions of Equation 20 through Equation 23 are satisfied. POWER MOSFETS For this example, the N-channel power MOSFETs have been selected for one high-side switch and two low-side switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3120A) dictates whether standard threshold or logic-level threshold MOSFETs must be used. With VGATE equal to approximately 10 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are recommended. The maximum output current (IO) determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. With the ADP3197, currents are balanced between phases; thus, the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, Equation 24 shows the total power that is dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO). () () SF DS SF R SF O SF R n I n n I D P × ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × + ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ × − = 2 2 12 1 1 (24) Knowing the maximum output current being designed for and the maximum allowed power dissipation, the user can find the required RDS(ON) for the MOSFET. For D-Pak MOSFETs up to an ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W at 120°C junction temperature. Thus, for this example (100 A maximum), RDS(SF) (per MOSFET) is less than 7.5 mΩ. This RDS(SF) is also at a junction temperature of about 120°C. As a result, users need to account for these conditions when selecting a low-side MOSFET. This example uses two lower-side MOSFETs at 4.8 mΩ, each at 120°C. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of the feedback to input needs to be small (less than 10% is recom- mended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. Also, the time to switch the synchronous MOSFETs off should not exceed the nonoverlap dead time of the MOSFET driver (40 ns typical for the ADP3110A). The output impedance of the driver is approximately 2 Ω and the typical MOSFET input gate resistances are about 1 Ω to 2 Ω. Therefore, a total gate capacitance of less than 6000 pF should be adhered to. |
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