Reset, Stop, Wait, Mode Select, and Interrupt Timing

56F802 Technical Data, Rev. 9

Freescale Semiconductor

25

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Figure 3-9 External Level-Sensitive Interrupt Timing

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

RESET Assertion to Address, Data and Control Signals High

Impedance

—

21

ns

OMR Bit 6 = 0

OMR Bit 6 = 1

2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:

• After power-on reset

• When recovering from Stop state

3. Parameters listed are guaranteed by design.

275,000T

128T

—

—

ns

ns

RESET De-assertion to First External Address Output

33T

34T

ns

Edge-sensitive Interrupt Request Width

1.5T

—

ns

General

Purpose

I/O Pin

IRQA

b) General Purpose I/O