BL808 datasheet(21/93 Pages) BOUFFALOALB

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BL808 Datasheet

– When the bit width is 16 bits, the depth of the FIFO is 16

– When the bit width is 8 bits, the depth of the FIFO is 32

• Support DMA transfer mode

2.10.4 I2C

The chip has four built-in I2C interfaces with the following features:

• Support multi-master mode and arbitration function

• The working clock can be selected as BCLK or XCLK

• With device address register, register address register, register address length can be set to 1 byte / 2 bytes / 3

bytes / 4 bytes

• I2C has independent transceiver FIFO, FIFO depth is 2 words

• Support DMA function

2.10.5 I2S

The chip has a built-in I2S interface with the following features:

• Support master mode and slave mode

• Support Left-justified/ Right-justified/ DSP and other data formats, the data width can be configured as 8/16/24/32

bits

• The working clock can be selected as BCLK or XCLK

• Supports both four-channel and six-channel modes in addition to mono/dual-channel mode

• Supports playback of mono audio dubbing to binaural mode

• Support dynamic mute switching function

• I2S has independent transceiver FIFO, FIFO depth is 16 words

• Support DMA function

2.10.6 EMAC

The EMAC module is a 10/100Mbps Ethernet Media Access Controller (Ethernet MAC) compatible with IEEE 802.3,

has the following characteristics:

• Compatible with the MAC layer defined by IEEE 802.3

• PHY supporting MII/RMII interface defined by IEEE 802.3

• Interacts with PHY through MDIO interface

BL808 Datasheet

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