AD9865BCPRL datasheet(37/48 Pages) AD

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AD9865

Rev. A | Page 37 of 48

CLOCK SYNTHESIZER

The AD9865 generates all its internal sampling clocks, as well as

two user-programmable clock outputs appearing at CLKOUT1

and CLKOUT2, from a single reference source as shown in

Figure 76. The reference source can be either a fundamental

frequency or an overtone quartz crystal connected between

OSCIN and XTAL with the parallel resonant load components

as specified by the crystal manufacturer. It can also be a TTL-

level clock applied to OSCIN with XTAL left unconnected.

The data rate, fDATA, for the Tx and Rx data paths must always be

equal. Therefore, the ADC’s sample rate, fADC, is always equal to

fDATA while the TxDAC update rate is a factor of 1, 2, or 4 of

fDATA, depending on the interpolation factor selected. The data

rate refers to the word rate and should not be confused with the

nibble rate in full-duplex interface.

÷2N

XTAL

÷2L

÷2R

2M CLK

MULTIPLIER

XTAL

OSCIN

CLKOUT2

CLKOUT1

TO ADC

TO TxDAC

Figure 76. Clock Oscillator and Synthesizer

The 2M CLK multiplier contains a PLL (with integrated loop

filter) and VCO capable of generating an output frequency that

is a multiple of 1, 2, 4, or 8 of its input reference frequency,

fOSCIN, appearing at OSCIN. The input frequency range of fOSCIN

is between 20 MHz and 80 MHz, while the VCO can operate

over a 40 MHz to 200 MHz span. For the best phase noise/jitter

characteristics, it is advisable to operate the VCO with a fre-

quency between 100 MHz and 200 MHz. The VCO output

drives the TxDAC directly such that its update rate, fDAC, is

related to fOSCIN by the following equation:

fDAC = 2M × fOSCIN

(10)

where M = 0, 1, 2, or 3.

M is the PLL’s multiplication factor set in Register 0x04. The

value of M is determined by the Tx path’s word rate, fDATA, and

digital interpolation factor, F, as shown in the following

equation:

M = log2 (F × fDATA/fOSCIN)

(11)

Note: if the reference frequency appearing at OSCIN is chosen

to be equal to the AD9865’s Tx and Rx path’s word rate, then M

is simply equal to log2(F).

The clock source for the ADC can be selected in Register 0x04

as a buffered version of the reference frequency appearing at

OSCIN (default setting) or a divided version of the VCO output

(fDAC). The first option is the default setting and most desirable

if fOSCIN is equal to the ADC sample rate, fADC. This option

typically results in the best jitter/phase noise performance for

the ADC sampling clock. The second option is suitable in cases

where fOSCIN is a factor of 2 or 4 less than the fADC. In this case,

the divider ratio, N, is chosen such that the divided down VCO

output is equal to the ADC sample rate, as shown in the

following equation:

fADC = fDAC/2N

(12)

where N = 0, 1, or 2.

Figure 77 shows the degradation in phase noise performance

imparted onto the ADC’s sampling clock for different VCO

output frequencies. In this case, a 25 MHz, 1 V p-p sine wave

was used to drive OSCIN, and the PLL’s M and N factors were

selected to provide an fADC of 50 MHz for VCO operating

frequencies of 50, 100, and 200 MHz. The RxPGA input was

driven with a near full-scale, 12.5 MHz input signal with a gain

setting of 0 dB. Operating the VCO at the highest possible

frequency results in the best narrow and wideband phase noise

characteristics. For comparison purposes, the clock source for

the ADC was taken directly from OSCIN when driven by a

50 MHz square wave.

FREQUENCY (MHz)

2.5

4.5

6.5

8.5

10.5

12.5

14.5

16.5

18.5

20.5

22.5

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

DIRECT

VCO = 50MHz

VCO = 100MHz

VCO = 200MHz

Figure 77. Comparison of Phase Noise Performance when ADC Clock Source

is Derived from Different VCO Output Frequencies

The CLK synthesizer also has two clock outputs appearing at

CLKOUT1 and CLKOUT2. They are programmable via

voltage levels appearing at these outputs are relative to DRVDD

and remain active during a hardware or software reset. Table 22

shows the SPI registers pertaining to the clock synthesizer.

CLKOUT1 is a divided version of the VCO output and can be

set to be a submultiple integer of fDAC (fDAC/2R, where R = 0, 1, 2,

or 3). Because this clock is actually derived from the same set of

dividers used within the PLL core, it is phase-locked to them

such that its phase relationship relative to the signal appearing

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