AD9865BCPRL datasheet(27/48 Pages) AD

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AD9865

Rev. A | Page 27 of 48

TXPGA CONTROL

The AD9865 also contains a digital PGA in the Tx path distri-

buted between the TxDAC and IAMP. The TxPGA is used to

control the peak current from the TxDAC and IAMP over a

7.5 dB and 19.5 dB span, respectively, with 0.5 dB resolution.

A 6-bit word is used to set the TxPGA attenuation according to

the mapping shown in Figure 58. The TxDAC gain mapping is

applicable only when Bit 0 of Register 0x0E is set, and only the

four LSBs of the 6-bit gain word are relevant.

6-BIT DIGITAL CODE (Decimal Equivalent)

–20

–16

–18

–14

–12

–10

–8

–6

–2

–4

–1

–17

–19

–15

–13

–11

–9

–7

–3

–5

TxDACs IOUTP OUTPUT

HAS 7.5dB RANGE

IAMPs IOUTN AND IOUTG

OUTPUTS HAS 19.5dB RANGE

Figure 58. Digital Gain Mapping of TxPGA

The TxPGA register can be updated via the PGA[5:0] port or

SPI port. The first method should be considered for fast updates

of the TxPGA register. Its operation is similar to the description

in the RxPGA Control section. The SPI port allows direct up-

date and readback of the TxPGA register via Register 0x0A with

an update rate limited to 1.6 MSPS (SCLK = 32 MHz). Bit 6 of

Table 17 lists the SPI registers pertaining to the TxPGA. The

TxPGA control register default setting is for minimum

attenuation (0 dBFS) with the PGA[5:0] port disabled for Tx

gain control.

Table 17. SPI Registers TxPGA Control

Address (Hex)

Bit

Description

0x0A

(6)

Enable TxPGA update via SPI

(5:0)

TxPGA gain code

0x0B

(6)

Select TxPGA via PGA[5:0]

(5)

Select RxPGA via PGA[5:0]

0x0E

(0)

TxDAC output (IAMP disabled)

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