56F8023_07 datasheet(39/156 Pages) FREESCALE

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Peripheral Memory-Mapped Registers

56F8023 Data Sheet, Rev. 3

Freescale Semiconductor

Preliminary

DAC 0

DAC0

X:$00 F1C0

4-20

DAC 1

DAC1

X:$00 F1D0

4-21

Comparator A

CMPA

X:$00 F1E0

4-22

Comparator B

CMPB

X:$00 F1F0

4-23

QSCI 0

SCI0

X:$00 F200

4-24

QSPI 0

SPI0

X:$00 F220

4-25

I2C

X:$00 F280

4-26

X:$00 F400

4-27

Table 4-7 Quad Timer A Registers Address Map

(TMRA_BASE = $00 F000)

Address Offset

TMRA0_COMP1

Compare Register 1

TMRA0_COMP2

Compare Register 2

TMRA0_CAPT

Capture Register

TMRA0_LOAD

Load Register

TMRA0_HOLD

Hold Register

TMRA0_CNTR

Counter Register

TMRA0_CTRL

Control Register

TMRA0_SCTRL

Status and Control Register

TMRA0_CMPLD1

Comparator Load Register 1

TMRA0_CMPLD2

Comparator Load Register 2

TMRA0_CSCTRL

Comparator Status and Control Register

TMRA0_FILT

Input Filter Register

Reserved

TMRA0_ENBL

Timer Channel Enable Register

TMRA1_COMP1

$10

Compare Register 1

TMRA1_COMP2

$11

Compare Register 2

TMRA1_CAPT

$12

Capture Register

TMRA1_LOAD

$13

Load Register

TMRA1_HOLD

$14

Hold Register

TMRA1_CNTR

$15

Counter Register

TMRA1_CTRL

$16

Control Register

TMRA1_SCTRL

$17

Status and Control Register

TMRA1_CMPLD1

$18

Comparator Load Register 1

TMRA1_CMPLD2

$19

Comparator Load Register 2

TMRA1_CSCTRL

$1A

Comparator Status and Control Register

Table 4-6 Data Memory Peripheral Base Address Map Summary (Continued)

Peripheral

Prefix

Base Address

Table Number

56F8023 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

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