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SL2S3103FUD Datasheet(PDF) 7 Page - NXP Semiconductors |
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SL2S3103FUD Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 80 page ![]() NXP Semiconductors SL2S3103 ICODE 3 97pF 6 Wafer layout not to scale! GND LA LB TP Figure 2. SL2S3103FUD wafer layout and pin configuration for the bare die 6.1 Pin description Symbol Description LA Antenna connection LA LB Antenna connection LB GND Ground (disconnected from internal circuitry) TP Test pin (disconnected from internal circuitry) Table 2. Bonding pad description Refer to [5]. SL2S3103 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3.1 — 29 May 2024 Document feedback 7 / 80 |
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