Analog Integrated Circuit Device Data

Freescale Semiconductor

21

33977

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

This section provides a description of the 33977 SPI

behavior. To follow the explanation below, please refer to

Table 7 and to the timing diagrams illustrated in Figure 11

and Figure 12.

Figure 11. Single 16-Bit Word SPI Communication

Figure 12. Multiple 16-Bit Word SPI Communication

DATA INPUT

The Input Shift register captures data at the falling edge of

the SCLK. The SCLK pulses exactly 16 times only inside the

transmission windows (CS in a Logic [1] state). By the time

the CS signal goes to Logic [1] again, the contents of the

Input Shift register are transferred to the appropriate internal

register addressed in bits 15:13. The minimum time CS

should be kept high depends on the internal clock speed,

specified in the SPI Interface Timing section of the [Static

replaced with Dynamic - correcting table location] Dynamic

Electrical Characteristics, Table 4. It must be long enough so

the internal clock is able to capture the data from the Input

Shift register and transfer it to the internal registers.

DATA OUTPUT

At the first rising edge of the SCLK [clock deleted to

eliminate redundancy], with CS at Logic [1], the contents of

the selected Status Word register are transferred to the

Output Shift register. The first 16 bits clocked out are the

status bits. If data continues to clock in before the CS

transitions to Logic [1], the device begins to shift out the data

previously clocked in FIFO after the CS first transitioned to

Logic[1].

COMMUNICATION MEMORY MAPS AND

REGISTER DESCRIPTIONS

The 33977 device is capable of interfacing directly with a

microcontroller via the 16-bit SPI protocol specified below.

Table 7. Data Transfer Timing

Pin

Description

CS (1-to-0)

SO pin is enabled

CS (0-to-1)

33977 configuration and desired output states are transferred and executed according to the data in the Shift registers

SO

Will change state on the rising edge of the SCLK pin signal

SI

Will accept data on the falling edge of the SCLK pin signal

Output Shift register is loaded here

Note: SO is tri-stated when CS is Logic [1]

CS

CS

SCLK

SI

SO

D12

D11

0D12 OD

Notes:

1. SO is tri-stated when CS is Logic [1].

2. D15, D14, D13, , and D0 refer to the first 16 bits of data into the 33977.

3. D15*, D14*, D13*,. . . ., and D0* refer to the most recent entry of program data into the 33977.

4. OD15, OD14, OD13, . . .,and OD0 refer to the first 16 bits of fault and status data out of the 33977.

D2