XRT86L30IB datasheet(27/279 Pages) EXAR

27 / 279 page

XRT86L30

REV. 1.0.0

SINGLE T1/E1/J1 FRAMER/LIU COMBO

108

Microprocessor Interface—Chip Select Input:

The Microprocessor/Microcontroller must assert this input pin (toggle it "Low") in

order to exchange data with the Framer.

Note: For the 68K MPU, this signal is generated by address decode and

address strobe.

Microprocessor Interface—Read Strobe Input:

The exact behavior of this pin depends upon the type of Microprocessor/Micro-

controller the Framer has been configured to interface to, as defined by the

µPTYPE[2:0] pins.

107

Microprocessor Interface—Write Strobe Input

The exact behavior of this pin depends upon the type of Microprocessor/Micro-

controller the Framer has been configured to interface to, as defined by the

µPTYPE[2:0] pins.

ACK0

ACK1

DMA Cycle Acknowledge Input—DMA Controller 0 (Write):

The external DMA Controller will assert this input pin “Low” when the following

two conditions are met:

a. After the DMA Controller, within the Framer has asserted (toggled “Low”), the

Req_0 output signal.

b. When the external DMA Controller is ready to transfer data from external

memory to the selected Transmit HDLC buffer.

At this point, the DMA transfer between the external memory and the selected

Transmit HDLC buffer may begin.

After completion of the DMA cycle, the external DMA Controller will negate this

input pin after the DMA Controller within the Framer has negated the Req_0 out-

put pin. The external DMA Controller must do this in order to acknowledge the

end of the DMA cycle.

DMA Cycle Acknowledge Input—DMA Controller 1 (Read):

The external DMA Controller asserts this input pin “Low” when the following two

conditions are met:

a. After the DMA Controller, within the Framer has asserted (toggled "Low"), the

Req_1 output signal.

b. When the external DMA Controller is ready to transfer data from the selected

Receive HDLC buffer to external memory.

At this point, the DMA transfer between the selected Receive HDLC buffer and

the external memory may begin.

After completion of the DMA cycle, the external DMA Controller will negate this

input pin after the DMA Controller within the Framer has negated the Req_1 out-

put pin. The external DMA Controller will do this in order to acknowledge the

end of the DMA cycle.

BLAST

100

Last Cycle of Burst Indicator Input:

The Microprocessor asserts this pin “Low”when it is performing its last read or

write cycle, within a burst operation.

RESET

Hardware Reset Input

Reset is an active low input. If this pin is pulled “Low” for more than 10

µS, the

device will be reset, and the internal registers will be reset to their default val-

ues.

MICROPROCESSOR INTERFACE

(Framer Channel Number indicated by )

SIGNAL NAME

PIN #TYPE

DESCRIPTION

XRT86L30IB Datasheet(PDF) 27 Page - Exar Corporation

XRT86L30IB Datasheet(HTML) 27 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL