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SP7652ERL/TR Datasheet(PDF) 9 Page - Sipex Corporation |
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SP7652ERL/TR Datasheet(HTML) 9 Page - Sipex Corporation |
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9 / 16 page  9 Rev F: /0/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation APPLICATIONS INFORMATION tors. However, exercise additional caution whentantalumcapacitorsareused.Tantalum capacitors are known for catastrophic failure when exposed to surge current, and input capacitors are prone to such surge current when power supplies are connected “live” to low impedance power sources. Loop Compensation Design The open loop gain of the whole system can be divided into the gain of the error ampli- fier, PWM modulator, buck converter output stage,andfeedbackresistordivider.Inorder tocrossoverattheselectedfrequencyFCO, the gain of the error amplifier compensates for the attenuation caused by the rest of the loop at this frequency. Thegoalofloopcompensationistomanipu- late loop frequency response such that its gain crosses over 0db at a slope of -20db/ dec. The first step of compensation design is to pick the loop crossover frequency. High crossover frequency is desirable for fasttransientresponse,butoftenjeopardizes the system stability. Crossover frequency should be higher than the ESR zero but less than /5 of the switching frequency. The ESR zero is contributed by the ESR associated with the output capacitors and can be determined by: ƒz(ESR) = . 2π COUT RESR The next step is to calculate the complex conjugate poles contributed by the LC output filter, ƒP(LC) = 2π L COUT When the output capacitors are of a Ceramic Type,theSP7652EvaluationBoardrequires aTypeIIIcompensationcircuittogiveaphase boostof180°inordertocounteracttheeffects of an underdamped resonance of the output filter at the double pole frequency. SP7652 Voltage Mode Control Loop with Loop (sRz2Cz2+1)(sR1Cz3+1) (sR esR CoUT + 1) [s^2LC oUT +s(R esR +R DC) C oUT +1] vin sR1Cz2(sRz3Cz3+1)(sRz2Cp1+1) vRAMP_PP voUT (volts) + _ vReF (volts) notes: R esR = output Capacitor equivalent series Resistance. R DC = output inductor DC Resistance. v RAMP_PP = sP6132 internal RA MP Amplitude Peak to Peak v oltage. Condition: Cz2 >> Cp1 & R1 >> Rz3 output Load Resistance >> R esR & R DC R 2 vReF (R 1 + R2) or voUT vFBK (volts) Type iii v oltage Loop Compensation G AMP (s) Gain Block PWM stage G PWM Gain Block output stage G oUT (s) Gain Block voltage Feedback G FBK Gain Block Definitions: RESR = Output Capacitor Equivalent Series Resistance RDC = Output Inductor DC Resistance RRAMP_PP = SP7652 internal RAMP Amplitude Peak to Peak Voltage Conditions: CZ2 >> Cp and R >> RZ3 Output Load Resistance >> RESR and RDC ∆Vin=iOut(max) RESR(cin)+ IOut(max) VOut (Vin-VOut) FScinVin2 The capacitor type suitable for the output ca- pacitorscanalsobeusedfortheinputcapaci- |
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