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SP7652ERL/TR Datasheet(PDF) 5 Page - Sipex Corporation |
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SP7652ERL/TR Datasheet(HTML) 5 Page - Sipex Corporation |
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5 / 16 page  5 Rev F: /0/06 SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator © Copyright 2006 Sipex Corporation UVLO fault is detected, the SP7652 is forced into an idle state where the output drivers are held off for a finite period before a re-start is attempted. Soft Start Soft start is achieved when a power con- verter ramps up the output voltage while controlling the magnitude of the input sup- ply source current. In a modern step down converter, ramping up the positive terminal of the error amplifier controls soft start. As a result, excess source current can be defined as the current required to charge the output capacitor. IVin = COut * (∆VOut / ∆TSOft-StaRt) The SP7652 provides the user with the op- tion to program the soft start rate by tying a capacitor from the SS pin to GND. The selection of this capacitor is based on the 0uA pull up current present at the SS pin and the 0.8V reference voltage. Therefore, the excess source can be redefined as: IVin = COut * (∆VOut *0µA / (CSS * 0.8V) Under Voltage Lock Out (UVLO) The SP7652 contains two separate UVLO comparators to monitor the internal bias (Vcc) and conversion (Vin) voltages independently. The Vcc UVLO threshold is internally set to 4.25V, whereas the Vin UVLO threshold is programmable through the UVIN pin. When the UVIN pin is greater than 2.5V, the SP7652 is permit- ted to start up pending the removal of all other faults. Both the Vcc and Vin UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault. Thermal and Short-Circuit Protection Because the SP7652 is designed to drive largeoutputcurrent,thereisachancethatthe power converter will become too hot. There- fore, an internal thermal shutdown (145°C) has been included to prevent the IC from malfunctioning at extreme temperatures. A short-circuit detection comparator has also been included in the SP7652 to protect against an accidental short at the output of the power converter. This comparator constantly monitors the positive and nega- tive terminals of the error amplifier, and if the Vfb pin falls more than 250mV (typical) below the positive reference, a short-circuit fault is set. Because the SS pin overrides the internal 0.8V reference during soft start, the SP7652 is capable of detecting short-circuit faults throughout the duration of soft start as well as in regular operation. Handling of Faults Upon the detection of power (UVLO), ther- mal, or short-circuit faults, the SP7652 is forced into an idle state where the SS and COMP pins are pulled low and the NFETS are held off. In the event of UVLO fault, the SP7652 remains in this idle state until the UVLO fault is removed. Upon the detection of a thermal or short-circuit fault, an internal 200ms timer is activated. In the event of a short-circuit fault, a re-start is attempted im- mediately after the 200ms timeout expires. Whereas, when a thermal fault is detected, the200msdelaycontinuouslyrecyclesanda re-startcannotbeattempteduntilthethermal fault is removed and the timer expires. Error Amplifier and Voltage Loop Since the heart of the SP7652 voltage error loop is a high performance, wide bandwidth transconductance amplifier, great care shouldbetakentoselecttheoptimalcompen- sation network. Because of the amplifier’s current limited (±150µA) transconductance, there are many ways to compensate the voltage loop or to control the COMP pin ex- ternally. If a simple, single-pole, single-zero response is desired, then compensation can be as simple as an RC circuit to Ground. If a more complex compensation is required, then the amplifier has enough bandwidth (45°C at 4 MHz) and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase margins at cross- THEORY OF OPERATION |
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