Advance Information

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

21

©200 Silicon Storage Technology, Inc.

S71292-00-000

1/06

REGISTERS

There are five types of registers available on the

SST49LF00xC, the multi-byte Read/Write configuration

registers, General Purpose Inputs registers, Block Locking

registers, Security ID register, and the JEDEC ID registers.

These registers appear at their respective address location

in the 4 GByte system memory map. Unused register loca-

tions will read as 00H. Any attempt to read or write any reg-

ister during an internal Write operation will be ignored.

Read or write access to the register during an internal Pro-

gram/Erase operation will be completed as follows:

•

Multi-byte Read/Write Configuration registers,

General Purpose Inputs register, and Block Lock-

ing registers can be accessed normally

•

Security ID register and the JEDEC ID registers

can not be accessed (reading these registers will

return unused register data 00H).

Multi-Byte Read/Write Configuration Reg-

isters (Firmware Memory Cycle)

The multi-byte read/write configuration (MBR) registers are

four 8-bit read-only registers located at addresses

FFBC0005-FFBC0008 for boot configured device (see

Table 13). These registers are accessible using Firmware

Memory Read cycle only. These registers contain informa-

tion about multi-byte read and write access sizes that will

be accepted for Firmware Memory multi-byte Read com-

mands. The registers are not available in AAI mode.

In case of multi-byte Firmware Memory register reads, the

device will return register data for the addressed register

until the command finishes, or is aborted.

General Purpose Inputs Register

The General Purpose Inputs register (GPI_REG) passes

the state of GPI[4:0] pins on the SST49LF00xC. It is rec-

ommended that the GPI[4:0] pins be in the desired state

before LFRAME# is brought low for the beginning of the

bus cycle, and remain in that state until the end of the cycle.

There is no default value since this is a pass-through regis-

ter. The GPI_REG register for the boot device appears at

FFBC0100H in the 4 GByte system memory map, and will

appear elsewhere if the device is not the boot device (see

Table 12). This register is not available to be read when the

device is in an Erase/Program operation. In case of multi-

byte Firmware Memory cycle register reads, the device will

return register data for the addressed register until the com-

mand finishes, or is aborted.

Register

1. Address shown in this column is for boot device only.

Address locations should appear elsewhere in the 4

GByte system memory map depending on ID strapping

values on ID[3:0] pins according with multiple device

selection mechanism.

Default

Value

Access

GPI_REG

FFBC 0100H

N/A

R

T12.0 1292

Register

1. Address shown in this column is for boot device only. Address locations should appear elsewhere in the 4 GByte system memory

map depending on ID strapping values on ID[3:0] pins when multiple LPC memory devices are used in a system.

Data

Access

Description

MULTI_BYTE_READ_L

FFBC 0005H

0100 1011b

R

Device supports 1,2,4, 16, 128 Byte reads

MULTI_BYTE_READ_H

FFBC 0006H

0000 0000b

R

Future Expansion for Read

MULTI_BYTE_WRITE_L

FFBC 0007H

0000 0011b

R

Device supports 1, 2, 4 Byte Write

MULTI_BYTE_WRITE_H

FFBC 0008H

0000 0000b

R

Future Expansion for Write

T13.0 1292