SST49LF004C datasheet(13/36 Pages) SST

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Advance Information

4 Mbit / 8 Mbit LPC Serial Flash

SST49LF004C / SST49LF008C

S71292-00-000

1/06

FIRMWARE MEMORY CYCLES

Firmware Memory Read Cycle

FIGURE 5: FIRMWARE MEMORY READ CYCLE WAVEFORM

TABLE

4: FIRMWARE MEMORY READ CYCLE FIELD DEFINITIONS

Clock

Cycle

Field

Name

Field Contents

LAD[3:0]1

1. Field contents are valid on the rising edge of the present clock cycle.

LAD[3:0]

Direction

Comments

START

1101

LFRAME# must be active (low) for the part to respond.

Only the last start field (before LFRAME# transitions high)

will be recognized. The START field contents (1101b) indi-

cate a Firmware Memory Read cycle.

IDSEL

0000 to 1111

Indicates which

SST49LF00xC device should respond.

If the IDSEL (ID select) field matches the value of ID[3:0],

then that particular device will respond to the LPC bus

cycle.

3-9

MADDR

YYYY

These seven clock cycles make up the 28-bit memory

address. YYYY is one nibble of the entire address.

Addresses are transferred most-significant nibble first.

MSIZE

KKKK

The MSIZE field indicates how many bytes will be trans-

ferred during multi-byte operations.

Device will execute multi-byte read of 2MSIZE bytes.

SST49LF00xC supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4,

16, 128 Bytes), with KKKK=0000b, 0001b, 0010b, 0100b, or

0111b.

TAR0

1111

IN,

then Float

In this clock cycle, the master (Intel ICH) has driven the bus

to all ‘1’s and then floats the bus, prior to the next clock

cycle. This is the first part of the bus “turnaround cycle.”

TAR1

1111 (float)

Float,

then OUT

The

SST49LF00xC takes control of the bus during this

cycle.

RSYNC

0000 (READY)

OUT

During this clock cycle, the device generates a “ready sync”

(RSYNC) indicating that the device has received the input

data. The least-significant nibble of the least-significant byte

will be available during the next clock cycle.

14-A

DATA

ZZZZ

OUT

A=(13+2n+1); n = MSIZE

Least significant nibbles outputs first.

(A+1)

TAR0

1111

OUT,

then Float

In this clock cycle, the

SST49LF00xC drives the bus to all

ones and then floats the bus prior to the next clock cycle.

This is the first part of the bus “turnaround cycle.”

A=(13+2n+1); n = MSIZE

(A+2)

TAR1

1111 (float)

Float,

then IN

The host resumes control of the bus during this cycle.

A=(13+2n+1); n = MSIZE

T4.0 1292

1292 F03.0

LFRAME#

LAD[3:0]

1101b

0000b

A[23:20] A[19:16]

A[3:0]

A[7:4]

A[11:8]

A[15:12]

MADDR

Start

IDSEL

MSIZE

LCLK

A[27:24]

0000b

RSYNC

TAR1

TAR0

TAR

D0[7:4]

Tri-State

D0[3:0]

Dn[7:4]

Dn[3:0]

KKKKb

1111b

DATA

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