Full-Bridge PWM Gate Driver

A89505

10

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

PACKAGE OUTLINE DRAWINGS

ES Package, “-J” variant, 20-Pin QFN with Exposed Thermal Pad and Wettable Flank

For Reference Only –Not for Tooling Use

(

Reference Allegro DWG-0000222 Rev. 4 or JEDEC MO-220WGGD)

Dimensions in millimeters

NOT TO SCALE

Exact case and lead configuration at supplier discretion within limits shown

0.95

C

SEATING

PLANE

C

0.08

21×

20

20

2

1

1

2

20

2

1

A

A

B

C

D

D

C

4.00 BSC

2.45 ±0.10

4.00 BSC

2.45 ±0.10

4.10

0.30

0.50

4.10

0.75 ±0.05

0.50 BSC

0.40 ±0.10

0.25

2.60

2.60

B

PCB Layout Reference View

Terminal #1 mark area.

Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier

discretion).

Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to

meet application process requirements and PCB layout tolerances; when mounting

on a multilayer PCB, thermal vias at the exposed thermal pad land can improve

thermal dissipation (reference EIA/JEDEC Standard JESD51-5).

Coplanarity includes exposed thermal pad and terminals.

0.05 REF

+0.03

–0.02

0.40 ±0.10

0.05 REF

0.08 REF

0.203 REF

Detail A

DETAIL A

0.20

0.25

0.10

Standard Branding Reference View

Lines 1, 2, 3 = 6 characters

Line 1: Part Number

Line 2: 4 digit Date Code

Line 3: Characters 5, 6, 7, 8 of

Assembly Lot Number

Pin 1 Dot top left

Center align

XXXX

Date Code

Lot Number

1

E

Branding scale and appearance at supplier discretion.

E

C

0.15

2×

0.02

+0.05

–0.07