© 2005 Microchip Technology Inc.

DS21977B-page 11

MCP9805

4.1.2

SENSOR CONFIGURATION

REGISTER (CONFIG)

The MCP9805 has a 16-bit Configuration register

(CONFIG) that allows the user to set various functions

for a robust temperature monitoring system. Bits 10

thru 0 are used to select Event output boundary hyster-

esis, device Shutdown or Low-Power mode, tempera-

ture

boundary

and

critical

temperature

lock,

temperature Event output enable/disable. In addition,

the user can select the Event output condition (output

output polarity and mode (Comparator Output or Inter-

rupt Output mode).

The temperature hysteresis bits 10 and 9 can be used

to prevent output chatter when the ambient tempera-

ture gradually changes beyond the user-specified

temperature boundary (see Section 4.2.2 “Tempera-

ture Hysteresis (THYST)”. The Continuous Conversion

or Shutdown mode is selected using bit 8. In Shutdown

mode, the band gap temperature sensor circuit stops

converting temperature and the Ambient Temperature

temperature data (see Section 4.2.1 “Shutdown

Mode”). Bits 7 and 6 are used to lock the

to prevent an accidental rewrite. Bits 5 thru 0 are used

to configure the temperature Event output pin. All

functions

are

described

in

Register 4-3

(see

Section 4.2.3 “Event Output Configuration”).

REGISTER 4-3:

CONFIGURATION REGISTER (CONFIG)

→ ADDRESS ‘0000 0001’b

bit 15-11 Unimplemented: Read as ‘0’

bit 10-9

00

=

0°C (power-up default)

01

=

1.5°C

10

=

3.0°C

11

=

6.0°C

(Refer to Section 4.2.3 “Event Output Configuration”)

bit 8

Shutdown Mode (SHDN) bit:

0

= Continuous Conversion (power-up default)

1

= Shutdown (Low-Power mode)

In shutdown, all power-consuming activities are disabled, though all registers can be written to or read.

This bit cannot be set ‘1’ when either of the lock bits is set (bit 6 and bit 7). However, it can be cleared ‘0’

for Continuous Conversion while locked. (Refer to Section 4.2.1 “Shutdown Mode”)

bit 7

0

1

When enabled, this bit remains set ‘1’ or locked until cleared by internal reset (Section 4.3 “Summary of

Power-up Default”). This bit does not require a double-write.

.

Upper-Half:

U-0

U-0

U-0

U-0

U-0

R/W-0

R/W-0

R/W-0

——

—

—

—

SHDN

bit 15

bit 8

Lower-Half:

R/W-0

R/W-0

R/W-0

R-0

R/W-0

R/W-0

R/W-0

R/W-0

Crit. Lock

Win. Lock

Int. Clear

Event Stat. Event Cnt.

Event

Sel.

Event

Pol.

Event

Mod.

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown