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PIC18F85J11 Datasheet(PDF) 21 Page - Microchip Technology |
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PIC18F85J11 Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 396 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39774C-page 19 PIC18F85J11 FAMILY TABLE 1-4: PIC18F8XJ11 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description TQFP MCLR 9 I ST Master Clear (input) or programming voltage (input). This pin is an active-low Reset to the device. RA7/OSC1/CLKI RA7 OSC1 CLKI 49 I/O I I TTL CMOS CMOS Oscillator crystal or external clock input. General purpose I/O pin. Oscillator crystal input. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) RA6/OSC2/CLKO RA6 OSC2 CLKO 50 I/O O O TTL — — Oscillator crystal or clock output. General purpose I/O pin. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC modes, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. PORTA is a bidirectional I/O port. RA0/AN0 RA0 AN0 30 I/O I TTL Analog Digital I/O. Analog input 0. RA1/AN1 RA1 AN1 29 I/O I TTL Analog Digital I/O. Analog input 1. RA2/AN2/VREF- RA2 AN2 VREF- 28 I/O I I TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (low) input. RA3/AN3/VREF+ RA3 AN3 VREF+ 27 I/O I I TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (high) input. RA4/T0CKI RA4 T0CKI 34 I/O I ST/OD ST Digital I/O. Open-drain when configured as output. Timer0 external clock input. RA5/AN4 RA5 AN4 33 I/O I TTL Analog Digital I/O. Analog input 4. RA6 See the OSC2/CLKO/RA6 pin. RA7 See the OSC1/CLKI/RA7 pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (80-pin devices, Extended Microcontroller mode only). 2: Default assignment for CCP2 when CCP2MX Configuration bit is set. 3: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared. |
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