PIC18F44J10-ESLASHML datasheet(267/358 Pages) MICROCHIP

267 / 358 page

Preliminary

DS39682C-page 265

PIC18F45J10 FAMILY

LFSR

Load FSR

Syntax:

LFSR f, k

Operands:

≤ f ≤ 2

≤ k ≤ 4095

Operation:

→ FSRf

Status Affected:

None

Encoding:

1110

1111

1110

0000

00ff

k7kkk

k11kkk

kkkk

Description:

The 12-bit literal ‘k’ is loaded into the

File Select Register pointed to by ‘f’.

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode

Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Example:

LFSR 2, 3ABh

After Instruction

FSR2H

03h

FSR2L

ABh

MOVF

Move f

Syntax:

MOVF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

→ dest

Status Affected:

N, Z

Encoding:

0101

00da

ffff

Description:

The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’ (default).

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write W

Example:

MOVF

REG, 0, 0

Before Instruction

REG

22h

FFh

After Instruction

REG

22h

PIC18F44J10-E/ML Datasheet(PDF) 267 Page - Microchip Technology

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