PIC18F44J10-ESLASHML datasheet(269/358 Pages) MICROCHIP

269 / 358 page

Preliminary

DS39682C-page 267

PIC18F45J10 FAMILY

MOVLW

Move Literal to W

Syntax:

MOVLW k

Operands:

≤ k ≤ 255

Operation:

→ W

Status Affected:

None

Encoding:

0000

1110

kkkk

Description:

The eight-bit literal ‘k’ is loaded into W.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Write to W

Example:

MOVLW

5Ah

After Instruction

5Ah

MOVWF

Move W to f

Syntax:

MOVWF

f {,a}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W)

→ f

Status Affected:

None

Encoding:

0110

111a

ffff

Description:

Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f

≤ 95 (5Fh). See

Section 21.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

Example:

MOVWF

REG, 0

Before Instruction

4Fh

REG

FFh

After Instruction

4Fh

REG

4Fh

PIC18F44J10-E/ML Datasheet(PDF) 269 Page - Microchip Technology

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