PIC18F4685-ISLASHSP datasheet(256/484 Pages) MICROCHIP

256 / 484 page

PIC18F2682/2685/4682/4685

DS39761B-page 254

Preliminary

19.4

Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part, by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT2:ACQT0 and

ADCS2:ADCS0 bits in ADCON2 should be updated in

accordance with the clock source to be used in that

mode. After entering the mode, an A/D acquisition or

conversion may be started. Once started, the device

should continue to be clocked by the same clock

source until the conversion has been completed.

If desired, the device may be placed into the

corresponding Idle mode during the conversion. If the

device clock frequency is less than 1 MHz, the A/D RC

clock source should be selected.

Operation in the Sleep mode requires the A/D FRC

clock to be selected. If the ACQT2:ACQT0 bits are set

to ‘000’ and a conversion is started, the conversion will

be delayed one instruction cycle to allow execution of

the SLEEP instruction and entry to Sleep mode. The

IDLEN bit (OSCCON<7>) must have already been

cleared prior to starting the conversion.

19.5

Configuring Analog Port Pins

The ADCON1, TRISA, TRISB and TRISE registers all

configure the A/D port pins. The port pins needed as

analog inputs must have their corresponding TRIS bits

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

Note 1: When reading the PORT register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an

analog input. Analog levels on a digitally

configured

input

will

accurately

converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

3: The

PBADEN

bit

Configuration

reset as analog or digital pins by control-

ling how the PCFG0 bits in ADCON1 are

reset.

PIC18F4685-I/SP Datasheet(PDF) 256 Page - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 256 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL