PIC18F4685-ISLASHSP datasheet(257/484 Pages) MICROCHIP

257 / 484 page

Preliminary

DS39761B-page 255

PIC18F2682/2685/4682/4685

19.6

A/D Conversions

Figure 19-3 shows the operation of the A/D converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Figure 19-4 shows the operation of the A/D converter

after

the

GO/DONE

bit

has

been

set,

the

ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD

acquisition time is selected before the conversion

starts.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D Result register

pair will NOT be updated with the partially completed

A/D

conversion

sample.

This

means

the

ADRESH:ADRESL registers will continue to contain

the value of the last completed conversion (or the

last

value

written

the

ADRESH:ADRESL

registers).

After the A/D conversion is completed or aborted, a

2TAD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

FIGURE 19-3:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 19-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY - TAD

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion starts

On the following cycle:

Set GO/DONE bit

(Holding capacitor is disconnected)

Conversion starts

(Holding capacitor continues

acquiring input)

TACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

ADRESH:ADRESL is loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

On the following cycle:

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