| Electronic Components Datasheet Search |
|
PIC18F4685-I/SP Datasheet(PDF) 443 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC18F4685-I/SP Datasheet(HTML) 443 Page - Microchip Technology |
|
443 / 484 page ![]() © 2007 Microchip Technology Inc. Preliminary DS39761B-page 441 PIC18F2682/2685/4682/4685 FIGURE 27-11: PARALLEL SLAVE PORT TIMING (PIC18F4682/4685) TABLE 27-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4682/4685) Note: Refer to Figure 27-4 for load conditions. RE2/CS RE0/RD RE1/WR RD7:RD0 62 63 64 65 Param. No. Symbol Characteristic Min Max Units Conditions 62 TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TWRH2DTIWR ↑ or CS ↑ to Data–In Invalid (hold time) PIC18FXXXX 20 — ns PIC18LFXXXX 35 — ns VDD = 2.0V 64 TRDL2DTVRD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TRDH2DTIRD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ —3 TCY |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |