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PIC18F4685-I/SP Datasheet(PDF) 446 Page - Microchip Technology

Part # PIC18F4685-I/SP
Description  28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
PDF  484 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4685-I/SP Datasheet(HTML) 446 Page - Microchip Technology

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PIC18F2682/2685/4682/4685
DS39761B-page 444
Preliminary
© 2007 Microchip Technology Inc.
FIGURE 27-14:
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH,
TSSL2SCL
SS
↓ to SCK ↓ or SCK ↑ Input
TCY
—ns
71
TSCH
SCK Input High Time
Continuous
1.25 TCY + 30
—
ns
71A
Single Byte
40
—
ns
(Note 1)
72
TSCL
SCK Input Low Time
Continuous
1.25 TCY + 30
—
ns
72A
Single Byte
40
—
ns
(Note 1)
73
TDIV2SCH,
TDIV2SCL
Setup Time of SDI Data Input to SCK Edge
100
—
ns
73A
TB2B
Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40
—
ns
(Note 2)
74
TSCH2DIL,
TSCL2DIL
Hold Time of SDI Data Input to SCK Edge
100
—
ns
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
ns
PIC18LFXXXX
—
45
ns
VDD = 2.0V
76
TDOF
SDO Data Output Fall Time
—
25
ns
77
TSSH2DOZSS
↑ to SDO Output High-Impedance
10
50
ns
80
TSCH2DOV,
TSCL2DOV
SDO Data Output Valid after SCK Edge PIC18FXXXX
—
50
ns
PIC18LFXXXX
—
100
ns
VDD = 2.0V
83
TscH2ssH,
TscL2ssH
SS
↑ after SCK Edge
1.5 TCY + 40
—
ns
Note 1:
Requires the use of parameter 73A.
2:
Only if parameter 71A and 72A are used.
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71
72
73
74
75, 76
77
78
79
80
79
78
MSb
LSb
bit 6 - - - - - -1
bit 6 - - - -1
LSb In
83
Note:
Refer to Figure 27-4 for load conditions.
MSb In



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