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PIC18F4685-I/SP Datasheet(PDF) 444 Page - Microchip Technology |
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PIC18F4685-I/SP Datasheet(HTML) 444 Page - Microchip Technology |
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444 / 484 page ![]() PIC18F2682/2685/4682/4685 DS39761B-page 442 Preliminary © 2007 Microchip Technology Inc. FIGURE 27-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 73 74 75, 76 78 79 80 79 78 MSb LSb bit 6 - - - - - -1 LSb In bit 6 - - - -1 Note: Refer to Figure 27-4 for load conditions. MSb In Param No. Symbol Characteristic Min Max Units Conditions 73 TDIV2SCH, TDIV2SCL Setup Time of SDI Data Input to SCK Edge 100 — ns 74 TSCH2DIL, TSCL2DIL Hold Time of SDI Data Input to SCK Edge 100 — ns 75 TDOR SDO Data Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 76 TDOF SDO Data Output Fall Time — 25 ns 78 TSCR SCK Output Rise Time PIC18FXXXX — 25 ns PIC18LFXXXX — 45 ns VDD = 2.0V 79 TSCF SCK Output Fall Time — 25 ns 80 TSCH2DOV, TSCL2DOV SDO Data Output Valid after SCK Edge PIC18FXXXX — 50 ns PIC18LFXXXX — 100 ns VDD = 2.0V |
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