COP8SCE9HMT7 datasheet(55/70 Pages) NSC

55 / 70 page

11.0 MICROWIRE/PLUS (Continued)

12.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

S/ADD REG

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads As

All Ones)

xx80 to xx8F

Unused RAM Address Space (Reads

Undefined Data)

xx90 to xx9F

Reserved

xxA0

Port A Data Register

xxA1

Port A Configuration Register

xxA2

Port A Input Pins (Read Only)

xxA3

Reserved for Port A

xxA4

Port B Data Register

xxA5

Port B Configuration Register

xxA6

Port B Input Pins (Read Only)

xxA7

Reserved for Port B

xxA8

ISP Address Register Low Byte

(ISPADLO)

xxA9

ISP Address Register High Byte

(ISPADHI)

xxAA

ISP Read Data Register (ISPRD)

xxAB

ISP Write Data Register (ISPWR)

xxAC

Reserved

xxAD

Reserved

xxAE

Reserved

xxAF

High Speed Timers Control Register

(HSTCR)

xxB0 to xxB7

Reserved

xxB8

USART Transmit Buffer (TBUF)

xxB9

USART Receive Buffer (RBUF)

xxBA

USART Control and Status Register

(ENU)

xxBB

USART Receive Control and Status

Address

Contents

S/ADD REG

xxBC

USART Interrupt and Clock Source

xxBD

USART Baud Register (BAUD)

xxBE

USART Prescale Select Register (PSR)

xxBF

Reserved for USART

xxC0

Timer T2 Lower Byte

xxC1

Timer T2 Upper Byte

xxC2

Timer T2 Autoload Register T2RA Lower

Byte

xxC3

Timer T2 Autoload Register T2RA Upper

Byte

xxC4

Timer T2 Autoload Register T2RB Lower

Byte

xxC5

Timer T2 Autoload Register T2RB Upper

Byte

xxC6

Timer T2 Control Register

xxC7

WATCHDOG Service Register

(Reg:WDSVR)

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

xxC9

MIWU Enable Register (Reg:WKEN)

xxCA

MIWU Pending Register (Reg:WKPND)

xxCB to xxCE

Reserved

xxCF

Idle Timer Control Register (ITMR)

xxD0

Port L Data Register

xxD1

Port L Configuration Register

xxD2

Port L Input Pins (Read Only)

xxD3

Reserved for Port L

xxD4

Port G Data Register

xxD5

Port G Configuration Register

xxD6

Port G Input Pins (Read Only)

xxD7 to xxDB

Reserved

xxDC

Port H Data Register

xxDD

Port H Configuration Register

xxDE

Port H Input Pins (Read Only)

xxDF

Reserved for Port H

20032739

FIGURE 33. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High

COP8SCE9HMT7 Datasheet(PDF) 55 Page - National Semiconductor (TI)

COP8SCE9HMT7 Datasheet(HTML) 55 Page - National Semiconductor (TI)

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