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DSPIC30F3010AT-20E/ML Datasheet(PDF) 81 Page - Microchip Technology |
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DSPIC30F3010AT-20E/ML Datasheet(HTML) 81 Page - Microchip Technology |
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81 / 220 page  © 2007 Microchip Technology Inc. Confidential DS70141D-page 79 dsPIC30F3010/3011 12.2.2 INPUT CAPTURE IN CPU IDLE MODE CPU Idle mode allows input capture module operation with full functionality. In the CPU Idle mode, the interrupt mode selected by the ICI<1:0> bits are applicable, as well as the 4:1 and 16:1 capture prescale settings, which are defined by control bits ICM<2:0>. This mode requires the selected timer to be enabled. Moreover, the ICSIDL bit must be asserted to a logic ‘0’. If the input capture module is defined as ICM<2:0> = 111 in CPU Idle mode, the input capture pin will serve only as an external interrupt pin. 12.3 Input Capture Interrupts The input capture channels have the ability to generate an interrupt, based upon the selected number of capture events. The selection number is set by control bits ICI<1:0> (ICxCON<6:5>). Each channel provides an interrupt flag (ICxIF) bit. The respective capture channel interrupt flag is located in the corresponding IFSx status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The Capture Interrupt Enable bit is located in the corresponding IEC control register. |
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