DSPIC30F3010AT-20ESLASHML datasheet(98/220 Pages) MICROCHIP

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dsPIC30F3010/3011

DS70141D-page 96

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When the PWM time base is in the Up/Down Counting

mode with double updates, new duty cycle values are

updated when the value of the PTMR register is zero,

and when the value of the PTMR register matches the

value in the PTPER register. The contents of the duty

cycle buffers are automatically loaded into the duty

cycle registers when the PWM time base is disabled

(PTEN = 0).

15.6

Complementary PWM Operation

In the Complementary mode of operation, each pair of

PWM outputs is obtained by a complementary PWM

signal. A dead time may be optionally inserted during

device switching, when both outputs are inactive for a

short period (Refer to Section 15.7).

In Complementary mode, the duty cycle comparison

units are assigned to the PWM outputs as follows:

• PDC1 register controls PWM1H/PWM1L outputs

• PDC2 register controls PWM2H/PWM2L outputs

• PDC3 register controls PWM3H/PWM3L outputs

The Complementary mode is selected for each PWM

I/O pin pair by clearing the appropriate PMODx bit in the

PWMCON1 SFR. The PWM I/O pins are set to

Complementary mode by default upon a device Reset.

15.7

Dead-Time Generators

Dead-time generation may be provided when any of

the PWM I/O pin pairs are operating in the Comple-

mentary Output mode. The PWM outputs use Push-

Pull drive circuits. Due to the inability of the power out-

put devices to switch instantaneously, some amount of

time must be provided between the turn-off event of

one PWM output in a complementary pair and the turn-

on event of the other transistor.

The PWM module allows two different dead times to be

programmed. These two dead times may be used in

one of two methods described below to increase user

flexibility:

• The PWM output signals can be optimized for

different turn-off times in the high side and low

side transistors in a complementary pair of

transistors. The first dead time is inserted

between the turn-off event of the lower transistor

of the complementary pair and the turn-on event

of the upper transistor. The second dead time is

inserted between the turn-off event of the upper

transistor and the turn-on event of the lower

transistor.

• The two dead times can be assigned to individual

PWM I/O pin pairs. This Operating mode allows

the PWM module to drive different transistor/load

combinations with each complementary PWM I/O

pin pair.

15.7.1

DEAD-TIME GENERATORS

Each complementary output pair for the PWM module

has a 6-bit down counter that is used to produce the

dead-time insertion. As shown in Figure 15-4, each

dead-time unit has a rising and falling edge detector

connected to the duty cycle comparison output.

15.7.2

DEAD-TIME RANGES

The amount of dead time provided by the dead-time

unit is selected by specifying the input clock prescaler

value and a 6-bit unsigned value.

Four input clock prescaler selections have been pro-

vided to allow a suitable range of dead time, based on

the device operating frequency. The dead-time clock

prescaler values are selected using the DTAPS<1:0>

control bits in the DTCON1 SFR. One of four clock

prescaler options (TCY, 2TCY, 4TCY or 8TCY) may be

selected.

After the prescaler value is selected, the dead time is

adjusted by loading 6-bit unsigned values into the

DTCON1 SFR.

The dead-time unit prescaler is cleared on the following

events:

• On a load of the down timer due to a duty cycle

comparison edge event.

• On a write to the DTCON1 register.

• On any device Reset.

Note:

The user should not modify the DTCON1

value while the PWM module is operating

(PTEN = 1). Unexpected results may

occur.

DSPIC30F3010AT-20E/ML Datasheet(PDF) 98 Page - Microchip Technology

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