TSA5523MSLASHC1 datasheet(7/20 Pages) PHILIPS

7 / 20 page

1996 Dec 17

Philips Semiconductors

Product speciﬁcation

1.4 GHz I2C-bus controlled multimedia

synthesizer

TSA5523M

Table 3

Address selection

INPUT VOLTAGE APPLIED TO PIN AS

MA1

MA0

0 V to 0.1VCC1

open-circuit or 0.2VCC1 to 0.3VCC1

0.4VCC1 to 0.6VCC1

0.9VCC1 to VCC1

Table 4

Test bits

Table 5

Ratio select bits

Table 6

Band-switch output levels

DEVICE OPERATION

normal mode

charge-pump is OFF

charge-pump is sinking

current

charge-pump is sourcing

current

100

fref is available on P6 output

101

fdiv/2 is available on P6 output

RSA

RSB

REFERENCE DIVIDER

640

1024

512

OUTPUT

VOLTAGE

ON PIN BS

PHILIPS M/O

IC’s BAND

0.25 V

band A

0.4VCC1

band B

0.8VCC1

band C

111

VCC1

band C

all other codes

VCC1

band C

Read mode: R/W=1 (see Table 7)

Data can be read out of the device by setting the R/W bit

to logic 1. After the slave address has been recognized,

the device generates an acknowledge pulse and the first

data byte (status byte) is transferred on the SDA line

(MSB first). Data is valid on the SDA line during a HIGH

level of the SCL clock signal. A second data byte can be

read out of the device if the processor generates an

acknowledge on the SDA line (master acknowledge).

End of transmission will occur if no master acknowledge

occurs. The device will then release the data line to allow

the processor to generate a STOP condition. When Ports

P0 to P2 are used as inputs, the corresponding bits must

be logic 0 (high-impedance state). The Power-On Reset

flag (POR) is set to logic 1 at power-on. It is reset when an

end-of-data is detected by the device (end of a read

sequence). Control of the loop is made possible with the

in-lock flag FL (FL = 1) which indicates when the loop is

locked. The bits I2, I1 and I0 represent the status of the I/O

Ports P2, P1 and P0 respectively.

A logic 0 indicates a LOW level and a logic 1 indicates a

HIGH level (see threshold level in the “Characteristics”).

A built-in ADC is available on pin P6. This converter can be

used to feed AFC information to the controller from the IF

section of the television. The relationship between bits

A2, A1 and A0 is given in Table 9.

At power-on, the device is reset as follows: all ports are set

to the high-impedance state, except P4, P5 and P7 which

are set to logic 1. The tuning amplifier is in the

high-impedance state (OS = 1). The POR level is fixed to

× VBE (2.1 V typ.). If VCC1 goes below the POR level the

circuit is reset.

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