TAS2120 datasheet(39/63 Pages) TI

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Table 6-42. Clock Error detection control (continued)

CLK_ERR_PWR_EN

Setting

Enabled (default)

Table 6-43. Clock Halt Timer

CLK_HALT_TIMER[2:0]

Setting

000

Disabled (infinite time).

001

0.8 ms (default)

010

3.2 ms

011

34.1 ms

100

68.3 ms

101

256 ms

110

768 ms

111

1.3 s

Table 6-44. Clock error type description

Clock error type

Description

Status flag register

bit

IRQZ generation

Mask bit

Clock error

Clock error for any internal or external clocking

configuration errors. This bit will be set along with specific

clock errors detected in the rest of the table below except

for Pre-Power-up Clock errors.

INT_LTCH2[3]

INT_MASK2[3]

Pre-Power-up Clock error

Clock error detected during shutdown mode after clock

error is detected at end of CLK_HALT_TIMER.

INT_LTCH4[2]

INT_MASK4[2]

Clock ratio change error

Clock error detected due to on the fly change in FSYNC to

SBCLK ratio.

INT_LTCH2[2]

INT_MASK2[2]

Fs change error

Clock error detected due to on the fly change in FSYNC

clock frequency

INT_LTCH2[1]

INT_MASK2[1]

Fs invalid error

Clock error detected due to incorrect FSYNC clock

frequency

INT_LTCH2[0]

INT_MASK2[0]

Frame out of sync

Clock error detected due to Frame out of sync

INT_LTCH2[5]

INT_MASK2[5]

Internal PLL Clock error

Clock error detected due to internally generated clock

frequency error.

INT_LTCH2[4]

INT_MASK2[4]

The device also has a digital watchdog timer which monitors for errors in the internal digital state machine and

shuts down the device on detection of such errors. This error can also raise an interrupt on IRQZ pin and flag to

the host device of the error state.

6.4.8 Digital IO pins

TAS2120 supports 1.8V and 3.3V IO voltage supply based on the voltage applied on the IOVDD pin.

I2S digital input pin has an optional weak pull down to prevent the pin from floating. Pull downs are not enabled

during HW shutdown. The pull downs are disabled by default and can be enabled by setting the corresponding

Pull down enable bit high.

Table 6-45. Digital pin weak pull down

Pin Name

Pull down control register

name

SDOUT

SDOUT_PD_EN

SDIN

SDIN_PD_EN

FSYNC

FSYNC_PD_EN

SBCLK

SBCLK_PD_EN

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TAS2120

SLASFC6 – AUGUST 2024

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