TAS2120 datasheet(21/63 Pages) TI

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Table 6-8. Noise gate threshold

NG_TH_LVL[2:0]

Configuration

000

-85 dBFs

001

-90 dBFs

010

-95 dBFs

011

-100 dBFs

100 (default)

-105 dBFs

101

-110 dBFs

110

-115 dBFs

111

-120 dBFs

Table 6-9. Noise gate hysteresis timer

NG_HYST_TIMER[1:0]

Configuration

10 ms

01 (default)

50 ms

100 ms

1000 ms

6.3.1.4.2 Music Efficiency Mode

When the Music efficiency mode feature is enabled, the device automatically detects low-power signal states

during active playback mode and reduces the overall IQ power consumption to extend the battery life. This

feature is useful for dynamic audio signals with varying signal levels for example music tracks, voice calls movie

tracks, and so forth.

The device monitors the input audio signal level against the programmed Music efficiency threshold configured

by the MUSIC_EFF_MODE_THR[23:0] register. When the audio signal falls below the threshold, an internal

hysteresis timer is enabled. If the signal level remains below the configured MUSIC_EFF_MODE_THR[23:0] for

the entire duration of the MUSIC_EFF_MODE_TIMER[23:0], the device enters into the Music efficiency mode.

When the device is in Music efficiency mode, the MUSIC_EFF_STATUS bit is set as high and when the device

comes out of music efficiency mode, the status bit is set low.

When the signal level increases above the MUSIC_EFF_MODE_THR[23:0], the device automatically wakes up

the blocks in low IQ mode and continues playing out the audio input signals. The transition from Music efficiency

mode to normal operation occurs with minimal click and pop. While the device is in Music efficiency mode, the

audio channel performance is maintained and doesn't impact the output signal level or noise.

The MUSIC_EFF_MODE_THR[23:0] and MUSIC_EFF_MODE_TIMER[23:0] registers can be configured using

the PPC3 Software Section 6.4.1.

6.3.1.4.3 VDD Y-bridge

TAS2120 uses a Y-bridge output stage for switching the class-D output PWM voltage between the VDD

and PVDD supply. When the feature is enabled using EN_Y_BRIDGE_MODE set to high, the device will

automatically select the output voltage to switch the output PWM at. When the signal level is low, the output will

switch at VDD to enable higher system-level efficiency by reducing the class-D output switching voltage. When

the signal level is high, the output switches on the PVDD voltage rail set by the integrated Boost, or external

PVDD in the external PVDD mode of operation.

The device monitors the input audio signal level against the programmed Y-bridge mode threshold configured

by VDD_MODE_THR_LVL[23:0] register. When the audio signal falls below the threshold, an internal hysteresis

timer is enabled. If the signal level remains below the configured YBRIDGE_HYST_TIMER[1:0] for the entire

duration of the selected time, the device enters into the lower voltage VDD supply-based PWM switching mode.

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TAS2120

SLASFC6 – AUGUST 2024

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