ASM330LHBG1 datasheet(71/130 Pages) STMICROELECTRONICS

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9.48

I3C_BUS_AVB (62h)

I3C_BUS_AVB register (R/W)

Table 127. I3C_BUS_AVB register

0(1)

I3C_Bus_

Avb_Sel1

I3C_Bus_

Avb_Sel0

0(1)

PD_DIS_

INT1

1. This bit must be set to 0 for the correct operation of the device.

Table 128. I3C_BUS_AVB register description

I3C_Bus_Avb_Sel[1:0]

These bits are used to select the bus available time when I3C IBI is used.

Default value: 00

(00: bus available time equal to 50 µs (default);

01: bus available time equal to 2 µs;

10: bus available time equal to 1 ms;

11: bus available time equal to 25 ms)

PD_DIS_INT1

This bit allows disabling the INT1 pull-down.

(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed

to the INT1 pin or when the I3C dynamic address is assigned);

1: Pull-down on INT1 disabled (pull-down not connected))

Note:

The IBI (in-band interrupt) is continuously generated (each time a bus available condition is satisfied) until an

interrupt is served. The master should execute the interrupt service routine (ISR) at a time lower than the

configured bus available time, otherwise the master should disable the interrupt (I3C DISEC in order to disable

the interrupt request) at a time lower than the bus available time.

If the master needs more time to analyze and start the correct ISR, then the master can change the bus

available time from 50 µs (default) to a higher time.

ASM330LHBG1

DS14080 - Rev 1

page 71/130

ASM330LHBG1 Datasheet(PDF) 71 Page - STMicroelectronics