STAC9271 datasheet(20/223 Pages) IDT

20 / 223 page

STAC9271/9272/9273/9274

10-CHANNEL HIGH DEFINITION AUDIO CODEC

PC AUDIO

IDT™

10-CHANNEL HIGH DEFINITION AUDIO CODEC

STAC9271/9272/9273/9274 V 1.0 MARCH2007

IDT CONFIDENTIAL

1. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz

bandwidth.

2. ± 3dB limits for Line Output and 0dB gain, at -20dBV

3. Amplitude of THD+N, measured with A-weighting filter, over 20 Hz to 20 KHz bandwidth.

4. Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz

bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio.)

5. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency.

6. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a

bandwidth 28.8 KHz to 100 KHz, with respect to a 1 Vrms DAC output.

8. Can be set to 0.5 or 0.8 AVdd.

40dB Mic Boost Enabled THD+N

5 mV Input

All

Power Supply

Power Supply Rejection Ratio

1 KHz

All

-70

Power Supply Rejection Ratio

20 KHz

All

-40

D0 Didd

3.3 V

D0 Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

D1 Didd

3.3 V

D1 Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

D2 Didd

3.3 V

D2 Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

D3 Didd

3.3 V

D3 Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

One Stereo ADC Didd

3.3 V

One Stereo ADC Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

One Stereo DAC Didd

3.3 V

One Stereo DAC Aidd

5.0 V, 4.5 V, & 4.0 V, 3.3 V

CD Input

CD Common Mode Rejection (CMR)

All

Voltage Reference Outputs

VREFout (Note 8)

All

0.5 X

AVdd

-V

VREFILT (VAG)

All

0.45X

AVdd

Phased Locked Loop

PLL lock time

All

200

µsec

PLL (or Azalia Bit CLK) 24 MHz clock jitter

All

150

500

psec

Parameter

Conditions

AVdd

Min

Typ

Max

Unit

STAC9271 Datasheet(PDF) 20 Page - Integrated Device Technology

STAC9271 Datasheet(HTML) 20 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL