P4C167

Page 5 of 10

Document # SRAM106 REV A

Notes:

9. CE and WE must be LOW for WRITE cycle.

10. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11. Write Cycle Time is measured from the last valid address to the first

transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE

WE

WE

WE

Parameter

Symbol

–10

–12

–15

–20

–25

–35

–45

Min Max

Max

Max

Max

Max

Max

Max

Min

Min

Min

Min

Min

Min

t

WC

t

CW

t

AW

t

AS

Write Cycle Time

Chip Enable Time

to End of Write

Address Valid to

End of Write

Address Set-up

Time

t

WZ

t

DH

t

DW

t

AH

t

WP

Write Pulse Width

Address Hold Time

from End of Write

Data Valid to End

of Write

Data Hold Time

Write Enable to

Output in High Z

t

OW

Output Active from

End of Write

10

8

8

0

8

0

6

0

0

6

12

10

10

0

10

0

7

0

0

7

15

2

12

0

12

0

10

0

0

8

20

15

15

0

15

0

13

0

0

12

25

20

20

0

20

0

15

0

0

15

35

25

25

0

25

0

20

0

0

17

45

30

30

0

30

0

25

0

0

20

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

AC CHARACTERISTICS - WRITE CYCLE

(V

(2)