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CY2308
Document Number: 38-07146 Rev. *E
Page 2 of 15
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC
Table 1. Pin Definitions - 16 Pin SOIC
Pin
Signal
Description
1REF[1]
Input reference frequency, 5V tolerant input
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Clock output, Bank B
7
CLKB2[2]
Clock output, Bank B
8S2[3]
Select input, bit 2
9S1[3]
Select input, bit 1
10
CLKB3[2]
Clock output, Bank B
11
CLKB4[2]
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Clock output, Bank A
15
CLKA4[2]
Clock output, Bank A
16
FBK
PLL feedback input
9
16
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
Top View
Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Tri-State
Tri-State
PLL
Y
0
1
Driven
Tri-State
PLL
N
1
0
Driven[4]
Driven[4]
Reference
Y
1
1
Driven
Driven
PLL
N
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
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