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Process Highlights

f

Ball pad pitch:

0.35, 0.4, 0.5, 0.65, 0.75, 0.8, 1.0 mm

f

Die thickness (flip chip):

As thin as 70 μm

f

Die thickness (wirebond):

As thin as 50 μm

f

Ball diameter:

As required

f

Wirebond pitch (min):

40 μm in-line with roadmap to 25 μm

f

Bump pitch mass reflow:

60 μm in-line

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Thermal compression:

50 μm in-line

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Wirebond length (max):

5 mm (200 mils)

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Wirebond diameter (min):

0.7, 0.8, 0.9, 1.0 mil+ in gold, silver or copper wirebond diameters

f

Wafer diameter:

150, 200 & 300 mm wafers

FlipStack® CSP

Cross Sections

Standard Materials

f

Package substrate

▷ Laminate dielectric

⨠ HL832: NXA, NS, NS-LC, NSF-LCA

⨠ E679: FG, FGB, FGBS, GT, E700G, E705G,

DS7409HG, DS7409HGB(S),

DS7409HGB(LE), ELC4785GSB,

ELC4785THB, ELC4785THG

▷ Layer count (laminate): 2-6

f

Die attach

▷ Bottom die: Flip chip attached by mass reflow

or thermal compression

▷ Top die: Non-conductive epoxy, film

f

Wire type: Au, Cu or Ag

f

Encapsulant: Transfer molded epoxy

f

Underfill: Capillary or molded

f

Bumps (F/C die): Pb-free, eutectic, Cu pillar

f

Solder balls: Pb-free, eutectic

f

Device type: Silicon, SiGe, GaAs, glass (IPD film

on glass)

f

Marking: Laser

Capillary or molded

underfill options

2-6 Layer substrates

A

B

C

Eutectic or lead-free

solder ball options

Gold, silver or copper

wire options

D

Capillary or molded

underfill options

2-6 Layer substrates

A

B

C

Eutectic or lead-free

solder ball options

Gold, silver or copper

wire options

D

D

A

B

C

D

A

B

C