Package Structure

f

Fan-out package flip-chip

mounted on a high pin count

BGA substrate

f

RDL facilitates shorter D2D

interconnections between

multiple chips

Chip Integration

f

Integrates multiple chiplets

within a single package

f

Chiplets can be different

functional units, such as ASICs

or HBMs

Interposer-less Design

f

Eliminates the need for an

interposer, reducing complexity

and costs

Electrical Performance

f

Offers excellent electrical

performance due to shorter D2D

connections

f

Features less insertion loss,

better impedance control, and

lower warpage

High I/O Density

f

Supports high I/O counts (>1000)

f

Ideal for large package sizes and

networking/server applications

Substrate-SWIFT (S-SWIFT) technology, also known as Silicon Wafer

Integrated Fan-Out (on Substrate), is revolutionizing the world

of advanced packaging. By boosting I/O and circuit density while

shrinking the footprint and profile, S-SWIFT is the go-to solution for

both single-die and multi-die applications, perfectly aligning with the

escalating demand for higher IC integration in mobile and networking

devices.

S-SWIFTTM Technology

TECHNOLOGY SOLUTIONS

S-SWIFT stands out as a game-changer in heterogeneous IC packaging,

enabling high-performance, cost-effective integration of multiple chiplets

and memories. This technology not only increases I/O and circuit density

but also paves the way for advanced 3D structures, making it indispensable

for the next generation of mobile and networking applications.

Fan-Out Meets Substrate

An innovative alternative to 2.5D TSV, S-SWIFT is a fan-out package that

enhances chip performance and reduces costs. By flip-chip mounting chips

onto a high pin count ball grid array (BGA) substrate, and incorporating a

re-distribution layer (RDL) for shorter die-to-die (D2D) interconnections,

S-SWIFT treats the entire fan-out package as a single die. This intelligent

design is then mounted onto the BGA substrate, offering a cost-effective

alternative to traditional 2.5D Through Silicon Via (TSV) technology.A key

feature of S-SWIFT is its re-distribution layer (RDL), which enables shorter

die-to-die (D2D) interconnections between multiple chips. This design

effectively treats the entire fan-out package as a single die, which is then

mounted onto the BGA substrate.

By integrating these advanced features, S-SWIFT offers a cost-effective

alternative to traditional 2.5D Through Silicon Via (TSV) technology.

Key Features

S-SWIFTTM PACKAGING

CONSIDERATIONS

S-SWIFT is a revolutionary technology

transforming the semiconductor

industry. This advanced packaging

technology enables high-density

fan-out (HDFO), providing superior

performance, reliability and

cost-effectiveness.

FEATURES

f

Polymer dielectrics

f

Multi-die and large die capability

f

Large body package capability

f

High-density interconnects

f

Miniaturization

f

Cost efficiency

f

Thermal management

f

Integration flexibility

APPLICATIONS

f

High Performance Computing (HPC)

f

Heterogeneous integrarion

f

Functional chip integration (CPU/GPU)

f

System-on-Chip (SoC) partitioning

f

Multi-die configurations

f

3D PoP-compatible applications

f

High-performance mobile application

processors and baseband devices