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PPC405EP-3LB200CZ Datasheet(PDF) 9 Page - Applied Micro Circuits Corporation

Part # PPC405EP-3LB200CZ
Description  PowerPC 405EP Embedded Processor
PDF  50 Pages
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Manufacturer  AMCC [Applied Micro Circuits Corporation]
Direct Link  http://www.amcc.com
Logo AMCC - Applied Micro Circuits Corporation

PPC405EP-3LB200CZ Datasheet(HTML) 9 Page - Applied Micro Circuits Corporation

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PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
AMCC
9
Data Sheet
SDRAM Memory Controller
The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to two physical banks. Up to
256MB per bank are supported, up to a maximum of 512MB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Features include:
•
11x8 to 13x11 addressing for SDRAM (2 banks)
•
32-bit memory interface support
•
Programmable address compare for each bank of memory
•
Industry standard 168-pin DIMMS are supported (some configurations)
•
Up to 133MHz memory supported by the 266MHz processor
•
Up to 111MHz memory supported by the 333MHz processor
•
4MB to 256MB per bank
•
Programmable address mapping and timing
•
Auto refresh
•
Page mode accesses with up to 4 open pages
•
Power management (self-refresh)
External Peripheral Bus Controller (EBC)
•
Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals
•
Up to 66MHz operation
•
Burst and non-burst devices
•
8- and 16-bit byte-addressable data bus width support
•
Latch data on Ready, synchronous or asynchronous
•
Programmable 2K clock time-out counter with disable for Ready
•
Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0–31 burst wait states for first access and up to 7 wait states for subsequent accesses
- Programmable CSon, CSoff relative to address
- Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS
•
Programmable address mapping
•
Peripheral Device pacing with external “Ready”
DMA Controller
•
Supports memory-to-memory transfers
•
Four channels
•
Scatter/gather capability for programming multiple DMA operations
•
32-bit addressing
•
Address increment or decrement
•
Internal 32-byte data buffering capability



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