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405EX Datasheet(PDF) 39 Page - Applied Micro Circuits Corporation |
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405EX Datasheet(HTML) 39 Page - Applied Micro Circuits Corporation |
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39 / 67 page ![]() PPC405EX – PowerPC 405EX Embedded Processor Revision 1.09 - August 21, 2007 AMCC Proprietary 39 Preliminary Data Sheet PCI Express Interface (n = 0 and 1) PCIEnATB Analog Test Bus for manufacturing test. O CML PCIEnClkC PCIEnClkT Differential input for external reference clock. I CML PCIEnRExt PCIEnRExtG External reference resistor. Attach a 1.37 k Ω, 1% resistor between RExt and RExtG to provide the reference for both the bias currents and the impedance calibration circuitry. I/O CML PCIEnRx PCIEnRx Differential receiver for received serial data. I LVDS receiver PCIEnTx PCIEnTx Differential driver for transmitted serial data. O LVDS driver Interrupts Interface IRQ0:2 External interrupt requests. I/O 3.3V LVTTL 5 IRQ3:5 External interrupt requests. I/O 3.3V LVTTL 1, 5 IRQ6 External interrupt requests. I/O 3.3V LVTTL 5 IRQ7:9 External interrupt requests. I/O 3.3V LVTTL 1, 5 JTAG Interface TCK Test clock. I 3.3V LVTTL 1 TDI Test data in. I 3.3V LVTTL w/pull-up 1, 4 TDO Test data out. O 3.3V LVTTL TMS Test mode select. I 3.3V LVTTL w/pull-up 1 TRST Test reset. Must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EX. I 3.3V LVTTL w/pull-up 1, 5 Table 6. Signal Functional Description (Sheet 2 of 7) Notes: 1. Receiver input has hysteresis. 2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. Signal Name Description I/O Type Notes |
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