SC1480AEVB datasheet(8/23 Pages) SEMTECH

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 2003 Semtech Corp.

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SC1480A

POWER MANAGEMENT

Applications Information (Cont.)

The current sensing circuit actually regulates the

inductor valley current (see .igure 2). This means that if

the current limit is set to 3A, the peak current through

the inductor would be 3A plus the peak ripple current,

and the average current through the inductor would be

3A plus 1/2 the peak-to-peak ripple current. The

equations for setting the valley current and calculating

the average current through the inductor are shown

below:

ILIMIT

ILOAD

IPEAK

TIME

Valley Current-Limit Threshold Point

.igure 2: Valley Current Limiting

The equation for the current limit threshold is as follows:

10e

SENSE

ILIM

LIMIT

•

Where (referring to .igure 3 on Page 14) R

ILIM is R5 and

SENSE is the RDS(ON) of the bottom .ET of Q1.

.or resistor sensing, a sense resistor is placed between

the source of the bottom .ET of Q1 and PGND. The

current through the source sense resistor develops a

voltage that opposes the voltage developed across R

ILIM.

When the voltage developed across the R

SENSE resistor

reaches the voltage drop across R

ILIM, a positive

over-current exists and the high side MOS.ET will not be

allowed to turn on. When using an external sense

resistor R

SENSE is the resistance of the sense resistor.

The current limit circuitry also protects against negative

over-current (i.e. when the current is flowing from the

load to PGND through the inductor and bottom MOS.ET).

In this case, when the bottom MOS.ET is turned on, the

phase node, LX, will be higher than PGND initially. The

SC1480A monitors the voltage at LX, and if it is greater

than a set threshold voltage of 125mV (nom.) the

bottom MOS.ET is turned off. The device then waits for

approximately 2µs and then DL goes high for 300ns (typ.)

once more to sense the current. This repeats until

either the over-current condition goes away or the part

latches off due to output overvoltage (see Output

Overvoltage Protection).

Power Good Output (VTT)

The ower good is an open-drain output and requires a

pull-up resistor. When the output voltage is 10% above

or below its set voltage (RE.OUT), PGD gets pulled low. It

is held low until the output voltage returns to within 10%

of the output set voltage. PGD is also held low during

start-up and will not be allowed to transition high until

soft start is over (440 switching cycles) and the output

reaches 90% of its set voltage. There is a 5µs delay built

into the PGD circuitry to prevent false transitions.

Output Overvoltage Protection (VTT)

When the output exceeds 10% of the its set voltage

(RE.OUT) the low-side MOS.ET is latched on. It stays

latched on and the controller is latched off until reset

(see below). There is a 5µs delay built into the OV

protection circuit to prevent false transitions. Note: to

reset VTT from any fault, VCCA or RE.IN must be toggled.

Output Undervoltage Protection (VTT)

When the output is 20% below its set voltage (RE.OUT)

the output is latched in a tri-stated condition. It stays

latched and the controller is latched off until reset (see

below). There is a 5µs delay built into the UV protection

circuit to prevent false transitions. Note: to reset VTT

from a any fault, VCCA or RE.IN must be toggled.

POR, UVLO and Softstart

An internal power-on reset (POR) occurs when VCCA

exceeds 3V, starting up the internal biasing. VCCA

undervoltage lockout (UVLO) circuitry inhibits switching

and also inhibits the RE.OUT buffer. When VCCA rises

above 4.2V, the VCCA UVLO circuitry enables the RE.OUT

buffer, resets the fault latch and soft start timer, and

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