HT46R652 datasheet(12/47 Pages) HOLTEK

12 / 47 page

HT46R652

Rev. 1.00

December 19, 2006

service routine, the EMI bit and the corresponding bit of

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. If the stack is full, the interrupt request will not

be acknowledged, even if the related interrupt is en-

abled, until the stack pointer is decremented. If immedi-

ate service is desired, the stack should be prevented

from becoming full.

All these interrupts will generate a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the Program Memory. Only the contents

of the program counter is pushed onto the stack. If the

contents of the register or of the status register is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

External interrupts are triggered by a an edge transition

on INT0 or INT1, when the related interrupt request flag,

EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0, is set. The

trigger edge type, high to low, low to high, or both low to

high and or high to low is determined by configuration

option. After the interrupt is enabled, if the stack is not

full, and the external interrupt is active, a subroutine call

to location 04H or 08H occurs. The interrupt request

flag, EIF0 or EIF1, and EMI bits are all cleared to disable

other maskable interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ised by setting the Timer/Event Counter 0 interrupt re-

quest flag, T0F; bit 6 of INTC0, which is normally caused

by a timer overflow. After the interrupt is enabled, and if

the stack is not full, and the T0F bit is set, a subroutine

call to location 0CH occurs. The related interrupt re-

quest flag, T0F, is reset, and the EMI bit is cleared to dis-

able other maskable interrupts. Timer/Event Counter 1

is operated in the same manner but its related interrupt

request flag is T1F, bit 4 of INTC1, and its subroutine call

location is 10H.

The time base interrupt is initialised by setting the time

base interrupt request flag, TBF; bit 5 of INTC1, that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 14H occurs. The related

interrupt request flag, TBF, is reset and the EMI bit is

cleared to disable further maskable interrupts.

The real time clock interrupt is initialised by setting the

real time clock interrupt request flag, RTF; bit 6 of INTC1,

that is caused by a regular real time clock signal. After the

interrupt is enabled, and the stack is not full, and the RTF

bit is set, a subroutine call to location 18H occurs. The re-

lated interrupt request flag, RTF, is reset and the EMI bit

is cleared to disable further maskable interrupts.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1=enabled; 0=disabled)

EEI0

Controls the external interrupt 0 (1=enabled; 0=disabled)

EEI1

Controls the external interrupt 1 (1=enabled; 0=disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

EIF0

External interrupt 0 request flag (1=active; 0=inactive)

EIF1

External interrupt 1 request flag (1=active; 0=inactive)

T0F

Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

For test mode used only.

Must be written as

²0²; otherwise may result in unpredictable operation.

INTC0 (0BH) Register

Bit No.

Label

Function

ET1I

Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

ETBI

Controls the time base interrupt (1=enabled; 0:disabled)

ERTI

Controls the real time clock interrupt (1=enabled; 0:disabled)

3, 7

Unused bit, read as

²0²

T1F

Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

TBF

Time base request flag (1=active; 0=inactive)

RTF

Real time clock request flag (1=active; 0=inactive)

INTC1 (1EH) Register

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