TMS320DM6437 datasheet(9/309 Pages) TI

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TMS320DM6437

Digital Media Processor

SPRS345B – NOVEMBER 2006 – REVISED MARCH 2007

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 6.8

Section 6.8, Interrupts:

Table 6-22, C64x+ Interrupt Controller Registers:

Deleted 0x0180 0140 AEGMUX0 register row

Deleted 0x0180 0144 AEGMUX1 register row

Deleted 0x0180 01C0 EVTASRT register row

Section 6.9.3

Section 6.9.3, EMIFA Electrical Data/Timing:

Figure 6-14, Asynchronous Memory Read Timing for EMIF:

Updated/Changed parameter #3, tc(EMRCYCLE), EMIF read cycle time

Figure 6-15, Asynchronous Memory Write Timing for EMIF:

Updated/Changed parameter #15, tc(EMWCYCLE), EMIF write cycle time

Section 6.10.1.6

Section 6.10.1.6, VPFE Electrical Data/Timing:

Table 6-35, Timing Requirements for VPFE PCLK Master/Slave Mode:

Deleted the MAX value from parameter #1, tc(PCLK), Cycle time, PCLK

Section 6.10.2.3

Section 6.10.2.3, VPBE Electrical Data/Timing:

Table 6-42, Timing Requirements for VPBE CLK Inputs:

Deleted the MAX value from parameter #1, tc(PCLK), Cycle time, PCLK

Deleted the MAX value from parameter #5, tc(VPBECLK), Cycle time, VPBECLK

Section 6.13.2

Section 6.13.2, HPI Peripheral Register Description(s):

Table 6-55, HPI Control Registers:

Updated/Changed the COMMENTS description for the PWREMU_MGMT register.

Updated/Changed the COMMENTS description for the HPIC register.

Updated/Changed the COMMENTS description for the HPIA (HIPAW/HPIAR) registers.

Updated/Changed the associated HPIA footnote.

Section 6.15.1.2

Section 6.15.1.2, McASP0 Peripheral Register Description(s):

Table 6-72, McASP0 Data Registers:

Updated/Changed the McASP0 Data Registers "ACRONYM" name from "XRBUF0" to "RBUF/XBUF".

Section 6.16.2

Section 6.16.2, HECC Peripheral Register Description(s):

Added the following HECC register tables:

Table 6-75, HECC Control and Status Registers

Table 6-76, HECC Message Object Registers

Table 6-77, HECC Message Mailbox RAM

Table 6-78, HECC Message Mailbox n RAM Entries

Section 6.20

Section 6.20, Peripheral Component Interconnect (PCI):

Updated/Changed "... a PCI backplane via the ..." to "... PCI-compliant devices via the ..."

Section 6.20

Section 6.20, Peripheral Component Interconnect (PCI):

Section 6.20.1, PCI Device-Specific Information:

Updated/Changed Table 6-97, Default Values for PCI Configuration Registers

Section 6.20

Section 6.20, Peripheral Component Interconnect (PCI):

Section 6.20.2, PCI Peripheral Register Description(s):

Deleted PCI Configuration Registers table

Table 6-98:

Updated/Changed the table title from "PCI Back End Configuration Registers" to "PCI

Memory-Mapped Registers"

Updated/Changed all "Back End Application" DSP Access Register Names to "DSP"

Deleted 01C1 A038 PCIBCLKMGT row; now part of "Reserved" range

Added/Combined the DSP-to-PCI Address Translation Registers table to the end of Table 6-98, PCI

Memory-Mapped Registers

Updated/Changed all "PCI Address Substitute n Register" DSP Access Register Names from "Substitute"

to "Substituion"

Section 6.20

Section 6.20, Peripheral Component Interconnect (PCI):

Table 6-99, PCI Hook Configuration Registers:

Deleted 01C1 A398 PCICMDSTATPRG row; now "Reserved"

Deleted 01C1 A3A8 PCILRSTREG row; now "Reserved"

Deleted 01C1 A3B0 through 01C1 A3F8 rows; now part of "Reserved" range

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