PI7C8152B datasheet(5/90 Pages) PERICOM

5 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 5 of 90

October 16, 2003 – Revision 1.11

TABLE OF CONTENTS

INTRODUCTION .............................................................................................................................. 11

SIGNAL DEFINITIONS ................................................................................................................... 12

2.1

SIGNAL TYPES............................................................................................................................... 12

2.2

SIGNALS ........................................................................................................................................ 12

2.2.1

PRIMARY BUS INTERFACE SIGNALS.......................................................................... 12

2.2.3

CLOCK SIGNALS ............................................................................................................... 15

2.2.4

MISCELLANEOUS SIGNALS........................................................................................... 15

2.2.5

POWER AND GROUND..................................................................................................... 16

2.3

PIN LIST – 160-PIN MQFP.......................................................................................................... 16

PCI BUS OPERATION ..................................................................................................................... 17

3.1

TYPES OF TRANSACTIONS..................................................................................................... 17

3.2

SINGLE ADDRESS PHASE........................................................................................................ 18

3.3

DUAL ADDRESS PHASE........................................................................................................... 18

3.4

DEVICE SELECT (DEVSEL_L) GENERATION....................................................................... 19

3.5

DATA PHASE.............................................................................................................................. 19

3.6

WRITE TRANSACTIONS .......................................................................................................... 19

3.6.1

MEMORY WRITE TRANSACTIONS................................................................................ 20

3.6.2

MEMORY WRITE AND INVALIDATE............................................................................ 21

3.6.3

DELAYED WRITE TRANSACTIONS............................................................................... 21

3.6.4

WRITE TRANSACTION ADDRESS BOUNDARIES....................................................... 22

3.6.5

BUFFERING MULTIPLE WRITE TRANSACTIONS..................................................... 22

3.6.6

FAST BACK-TO-BACK WRITE TRANSACTIONS ......................................................... 23

3.7

READ TRANSACTIONS ............................................................................................................ 23

3.7.1

PREFETCHABLE READ TRANSACTIONS.................................................................... 23

3.7.2

NON-PREFETCHABLE READ TRANSACTIONS.......................................................... 23

3.7.3

READ PREFETCH ADDRESS BOUNDARIES ............................................................... 24

3.7.4

DELAYED READ REQUESTS .......................................................................................... 24

3.7.5

DELAYED READ COMPLETION ON TARGET BUS .................................................... 25

3.7.6

DELAYED READ COMPLETION ON INITIATOR BUS................................................ 25

3.7.7

FAST BACK-TO-BACK READ TRANSACTION ............................................................. 26

3.8

CONFIGURATION TRANSACTIONS ...................................................................................... 26

3.8.1

TYPE 0 ACCESS TO PI7C8152x ....................................................................................... 27

3.8.2

TYPE 1 TO TYPE 0 CONVERSION .................................................................................. 27

3.8.3

TYPE 1 TO TYPE 1 FORWARDING................................................................................. 29

3.8.4

SPECIAL CYCLES ............................................................................................................. 30

3.9

TRANSACTION TERMINATION.............................................................................................. 30

3.9.1

MASTER TERMINATION INITIATED BY PI7C8152x.................................................. 31

3.9.2

MASTER ABORT RECEIVED BY PI7C8152x................................................................. 32

3.9.3

TARGET TERMINATION RECEIVED BY PI7C8152x .................................................. 32

3.9.4

TARGET TERMINATION INITIATED BY PI7C8152x .................................................. 35

ADDRESS DECODING..................................................................................................................... 36

4.1

ADDRESS RANGES ................................................................................................................... 37

4.2

I/O ADDRESS DECODING ........................................................................................................ 37

4.2.1

I/O BASE AND LIMIT ADDRESS REGISTER................................................................ 38

4.2.2

ISA MODE........................................................................................................................... 38

4.3

MEMORY ADDRESS DECODING............................................................................................ 39

4.3.1

MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS ......................... 39

4.3.2

PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS................. 40

PI7C8152B Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation

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