MPC8280 datasheet(287/1386 Pages) FREESCALE

287 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-11

NOTE

Regarding Table 8-2:

•

For reads, the processor cleans or flushes during a snoop based on the

TBST input. The processor cleans for single-beat reads (TBST negated)

to emulate read-with-no-intent-to-cache operations.

•

Castouts and snoop copybacks are generally marked as non-global and

are not snooped (except for reservation monitoring). However, other

masters performing DMA write operations with the same TT encoding

and marked as a global WR operation (whether global or non-global)

00110

WR w/Kill

Burst

(non-GBL)

Castout, ca-op push, or

snoop copyback

Kill, cancel

reservation

Write, assert AACK and

TA.

01010

Read

Single-beat

read or burst

Single-beat

read

CI load, CI I-fetch or

nonprocessor master

Clean or flush

Read, assert AACK

and TA.

01110

Read with

intent to

modify

Burst

Load miss, store miss,

or I-fetch

Flush

Read, assert AACK

and TA.

10010

WR w/flush

atomic

Single-beat

write

Single-beat

write

stwcx.

Flush, cancel

reservation

Write, assert AACK and

10110

Reserved

Not

applicable

Not applicable

Illegal

11010

Read

atomic

Single-beat

read or burst

Single-beat

read

lwarx (CI load)

Clean or flush

Read, assert AACK

and TA

11110

Read with

intent to

modify

atomic

Burst

lwarx (load miss)

Flush

Read, assert AACK

and TA

00011

Reserved

—

Not applicable

Illegal

00111

Reserved

—

Not applicable

Illegal

01011

Read with

no intent to

cache

Single-beat

read or burst

Not applicable

Clean

Read, assert AACK

and TA

01111

Reserved

—

Not applicable

Illegal

1XX11

Reserved

for customer

—

Not applicable

Illegal

1 TT1 can be interpreted as a read-versus-write indicator for the bus.

2 This column specifies the TT encoding for the general 60x protocol. The processor generates or snoops only a subset of

those encodings.

Table 8-2. Transfer Type Encoding (continued)

TT[0–4]1

60x Bus Specification2

MPC8280 as Bus Master

MPC8280 as

Snooper

MPC8280

as Slave

Command

Transaction

Bus Trans.

Transaction Source

Action on Hit

Action on Slave Hit

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