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MPC8280 Datasheet(PDF) 288 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 288 Page - Freescale Semiconductor, Inc

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The 60x Bus
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
8-12
Freescale Semiconductor
will cancel an active reservation during a snoop hit in the reservation
register (independent of a snoop hit in the cache).
•
A non-processor read can cause the internal processor to invalidate the
corresponding cache line if it exists.
8.4.3.2
Transfer Code Signals TC[0–2]
The transfer code signals, TC[0–2], provide supplemental information about the corresponding address
(mainly regarding the source of the transaction). Note that TCx signals can be used with the TT[0–4] and
TBST to further define the current transaction.
8.4.3.3
TBST and TSIZ[0–3] Signals and Size of Transfer
As shown in Table 8-4, the transfer size signals (TSIZ[0–3]) and the transfer burst signal (TBST) together
indicate the size of the requested data transfer. These signals can be used with address bits A[27–31] and
the device port size to determine which portion of the data bus contains valid data for a write transaction
or which portion of the bus should contain valid data for a read transaction.
The MPC8280 uses four double word burst transactions for transferring cache blocks. For these
transactions, TSIZ[0–3] are encoded as 0b0010, and address bits A[27–28] determine which double-word
is sent first.
The MPC8280 supports critical-word-first burst transactions (double-word-aligned) from the processor.
The MPC8280 transfers the critical double word of data first, followed by the double words from
increasing addresses, wrapping back to the beginning of the eight-word block as required.
Table 8-3. Transfer Code Encoding for 60x Bus
TC[0–2]
60x Bus
Read
Write
000
Core data transaction
Any write
001
Core touch load
—
010
Core instruction fetch
—
011
Reserved
—
100
101
Reserved
110
DMA function code 0
111
DMA function code 1
Table 8-4. Transfer Size Signal Encoding
TBST
TSIZ[0–3]
Transfer Size
Comments
Source
Negated
0 0 0 1
1 Byte
Byte
Core and DMA
Negated
0 0 1 0
2 Bytes
Half word
Core and DMA



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