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MPC8280 Datasheet(PDF) 290 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 290 Page - Freescale Semiconductor, Inc

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The 60x Bus
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
8-14
Freescale Semiconductor
8.4.3.5
Effect of Alignment on Data Transfers
Table 8-6 lists the aligned transfers that can occur to and from the MPC8280. These are transfers in which
the data is aligned to an address that is an integer multiple of the size of the data. For example, Table 8-6
shows that 1-byte data is always aligned; however, a 4-byte word must reside at an address that is a
multiple of 4 to be aligned.
In Figure 8-6, Table 8-6, and Table 8-7, OP0 is the most-significant byte of a word operand and OP7 is the
least-significant byte.
The MPC8280 supports misaligned memory operations, although they may degrade performance
substantially. A misaligned memory address is one that is not aligned to the size of the data being
transferred (such as, a word read from an odd byte address). The MPC8280’s processor bus interface
supports misaligned transfers within a word (32-bit aligned) boundary, as shown in Table 8-7. Note that
the 4-byte transfer in Table 8-7 is only one example of misalignment. As long as the attempted transfer
does not cross a word boundary, the MPC8280 can transfer the data to the misaligned address within a
single bus transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus
transfers to access data that crosses a word boundary.
Table 8-6. Aligned Data Transfers
Program Transfer
Size
TSIZ[0–3]
A[29–31]
Data Bus Byte Lanes
D0...
...D31
D32...
...D63
B0
B1
B2
B3
B4
B5
B6
B7
Byte
00 01
0 0 0
OP01
1 OPn: These lanes are read or written during that bus transaction. OP0 is the most-significant byte of a word operand
and OP7 is the least-significant byte.
—2
2 —: These lanes are ignored during reads and driven with undefined data during writes.
——————
00 01
0 0 1
—
OP1
—
—
—
—
—
—
00 01
0 1 0
—
—
OP2
—
—
—
—
—
00 01
0 1 1
—
—
—
OP3
—
—
—
—
0 0 0 1
1 0 0
—
———
OP4
—
——
0 0 0 1
1 0 1
—
————
OP5
——
0 0 0 1
1 1 0
—
—————
OP6
—
0 0 0 1
1 1 1
—
——————
OP7
Half-Word
0 0 1 0
0 0 0
OP0
OP1
—
—————
00 10
0 1 0
—
—
OP2
OP3
—
—
—
—
0 0 1 0
1 0 0
—
———
OP4
OP5
——
0 0 1 0
1 1 0
—
—————
OP6
OP7
Word
01 00
0 0 0
OP0
OP1
OP2
OP3
—
—
—
—
01 00
1 0 0
—
—
—
—
OP4
OP5
OP6
OP7
Double-Word
0 0 0 0
0 0 0
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7



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