RTL2832U datasheet(39/53 Pages) REALTEK

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Realtek

RTL2832U

Datasheet

DVB-T COFDM Demodulator + USB 2.0

Track ID: JATR-2265-11

Rev. 1.4

10.3. I2C Master Control Registers (0040h-0053h)

10.3.1.

I2C Clock Register (I2CCR, 0040h-0043h)

Table 22. I

2C Clock Register (I2CCR, 0040h-0043h)

Bits

Access

Reset

Description

31:6

Reserved

5:0

13h

FD10. Frequency 10M Divisor and 0 are forbidden. 10M=Bus clock/(FD10+1).

When powered on, software must write FD10 to let the I2C controller generate a 10MHz

clock.

10.3.2.

I2C Master Control Register (I2CMCR, 0044h-0047h)

Table 23. I

2C Master Control Register (I2CMCR, 0044h-0047h)

Bits

Access

Reset

Description

IMUR. I2C Master Unit Reset

0: Normal

1: Reset the I2C Unit (only resets hardware FSM). This bit will self-clear to Zero after

reset complete

CS. Command Start

0: Stop. After completing a whole transaction, it returns to Zero

1: Start

29:25

RWL. Read/Write Data Length for Related Commands

Does not include the slave address byte in the FIFO register.

When accessed, the controller will parse the byte following the last start (or Sr) byte to

find the command type.

0: 1 byte

………

17: 24 bytes

TORE. Time-Out Register Enable

If TOR is required, the I2C rate must be constrained within 25kbps~400kbps.

This constraint is due to the time-out register bit.

RTL2832U Datasheet(PDF) 39 Page - Realtek Semiconductor Corp.

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