RT8100APQV datasheet(13/18 Pages) RICHTEK

13 / 18 page

RT8100A

Preliminary

DS8100A-01 August 2007

www.richtek.com

Feedback Loop Compensation

First, the ramp signal applied to the PWM comparator is

proportional to the input voltage provided via the RR pin.

This keeps the modulator gain constant when the input

voltage varies. Second, the inductance valley current

proportional signal is derived from the voltage drop across

the ESR of the inductance is added to the ramp signal.

This effectively creates an internal current control loop.

The resistor connected to the CSN pin sets the gain in the

current feedback loop. The following expression estimates

the required value of the current sense resistor depending

on the maximum load current and the value of the

inductance DCR.

DCR

MAX

CSN

1) Modulator Frequency Equations

RT8100A is a analogous current mode buck converter

using the high gain error amplifier with transconductance

(OTA, Operational Transconductance Amplifier), as Figure

6 shown.

The Transconductance :

Δ VM = (EA+) - (EA-) ; Δ IOUT = E/A output current.

OUT

ΔV

ΔI

Figure 6. OTA Topology

This transfer function of OTA is dominated by a higher DC

gain and the output filter (LOUT and COUT) with a double

pole frequency at FLC and a zero at FESR. The DC gain of

the modulator is the input voltage (VIN) divided by the peak

to peak oscillator voltage VRAMP.

OUT

EA+

EA-

OUT

P(LC)

The next step of compensation design is to calculate the

ESR zero. The ESR zero is contributed by the ESR

associated with the output capacitance. Note that this

requires that the output capacitor should have enough ESR

to satisfy stability requirements. The ESR zero of the

output capacitor expressed as follows :

ESR

OUT

Z(ESR)

= π

2) Compensation Frequency Equations

The compensation network consists of the error amplifier

and the impedance networks ZC and ZF as Figure 7 shown.

Figure 7. Compensation Loop

⎟

⎠

⎞

⎜

⎝

⎛

Figure 8 shows the DC-DC converter's gain vs. frequency.

The compensation gain uses external impedance networks

ZC and ZF to provide a stable, high bandwidth loop. High

crossover frequency is desirable for fast transient response,

but often jeopardize the system stability. In order to cancel

one of the LC filter poles, place FZ1 before the LC filter

resonant frequency. In the experience, place FZ1 at 10%

LC filter resonant frequency. Crossover frequency should

be higher than the ESR zero but less than 1/5 of the

switching frequency. The FP2 should be place at half the

switching frequency.

The first step is to calculate the complex conjugate poles

contributed by the LC output filter.

The output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The resonant frequency of the

LC filter expressed as follows :

REF

COMP

OUT

RT8100APQV Datasheet(PDF) 13 Page - Richtek Technology Corporation

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